參數(shù)資料
型號: FT245RQ-REEL
廠商: FTDI, Future Technology Devices International Ltd
文件頁數(shù): 36/37頁
文件大?。?/td> 0K
描述: IC USB TO PARALLEL FIFO 32-QFN
產(chǎn)品培訓模塊: USB Introduction
標準包裝: 1
應用: USB 至 FIFO 控制器
接口: USB,F(xiàn)IFO,(同步/異步)
電源電壓: 1.8 V ~ 5.25 V
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 標準包裝
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 634 (CN2011-ZH PDF)
配用: 768-1020-ND - MOD USB PARALLEL FIFO DEV FT245R
其它名稱: 768-1012-6
Copyright 2010 Future Technology Devices International Limited
8
Document No.: FT_000052
FT245R USB FIFO IC Datasheet Version 2.12
Clearance No.: FTDI# 39
Pin No.
Name
Type
Description
4
VCCIO
PWR
+1.8V to +5.25V supply to the FIFO Interface group pins (1...3, 5, 6, 9...14, 22,
23). In USB bus powered designs connect this pin to 3V3OUT pin to drive out at
+3.3V levels, or connect to VCC to drive out at 5V CMOS level. This pin can also
be supplied with an external +1.8V to +2.8V supply in order to drive outputs at
lower levels. It should be noted that in this case this supply should originate from
the same source as the supply to VCC. This means that in bus powered designs a
regulator which is supplied by the +5V on the USB bus should be used.
7, 18,
21
GND
PWR
Device ground supply pins
17
3V3OUT
Output
+3.3V output from integrated LDO regulator. This pin should be decoupled to
ground using a 100nF capacitor. The main use of this pin is to provide the internal
+3.3V supply to the USB transceiver cell and the internal 1.5kΩ pull up resistor on
USBDP. Up to 50mA can be drawn from this pin to power external logic if
required. This pin can also be used to supply the VCCIO pin.
20
VCC
PWR
+3.3V to +5.25V supply to the device core. (see Note 1)
25
AGND
PWR
Device analogue ground supply for internal clock multiplier
Table 3.2 Power and Ground Group
Pin No.
Name
Type
Description
8, 24
NC
No internal connection
19
RESET#
Input
Active low reset pin. This can be used by an external device to reset the
FT245R. If not required can be left unconnected, or pulled up to VCC.
26
TEST
Input
Puts the device into IC test mode. Must be tied to GND for normal
operation, otherwise the device will appear to fail.
27
OSCI
Input
Input 12MHz Oscillator Cell. Optional – Can be left unconnected for
normal operation. (see Note 2)
28
OSCO
Output
Output from 12MHZ Oscillator Cell. Optional – Can be left unconnected
for normal operation if internal Oscillator is used. (see Note 2)
Table 3.3 Miscellaneous Signal Group
Pin No.
Name
Type
Description
1
D0
I/O
FIFO Data Bus Bit 0
2
D4
I/O
FIFO Data Bus Bit 4
3
D2
I/O
FIFO Data Bus Bit 2
5
D1
I/O
FIFO Data Bus Bit 1
6
D7
I/O
FIFO Data Bus Bit 7
9
D5
I/O
FIFO Data Bus Bit 5
10
D6
I/O
FIFO Data Bus Bit 6
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