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參數(shù)資料
| 型號(hào)： | FT10001L6X |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC RESET TIMER 6-MICROPAK |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類(lèi)型： | 可編程計(jì)時(shí)器 |
| 電源電壓： | 1.8 V ~ 5 V |
| 電流 - 電源： | 200µA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | * |
| 包裝： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 安裝類(lèi)型： | * |
2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FT10001 Rev 1.0.1
5
FT10001
—
Reset
Timer
with
Fixed
Delay
and
Reset
Pulse
Functional Description
Default operation time N is 10s. If the DSR pin is pulled
HIGH prior to VCC ramp, the FT10001 enters Test Mode
and the reset output, /RST1, is immediately pulled LOW
for factory testing. The DSR pin MUST be forced to
GND during normal operation. The DSR pin should
never be driven HIGH or left to FLOAT during normal
operation. The DSR PIN state should never be changed
during device operation; it must be biased prior to
supplying the VCC supply. If there is a need to use the
DSR=VCC Test Mode, the /SR0 must be HIGH when
the DSR pin is moved from LOW to HIGH to enter Zero-
Second Factory-Test Mode. To return to the standard
10-second reset time, the same procedure must be
followed with DSR=GND. The DSR pin should never be
allowed to change state while the /SR0 pin is LOW.
Operation Modes
A low input signal on /SR0 starts the oscillator. There
are two scenarios for counting: short duration and long
duration. In the short-duration scenario, output /RST1 is
not affected. In the long-duration scenario, the output
/RST1 goes LOW after /SR0 has been held LOW for
10s. The /RST1 output returns to its original HIGH
state 530ms after time tREC has expired, regardless of
the state of /SR0. The /RST1 output is an open-drain
driver. When the count time exceeds time 10s, the
/RST1 output pulls LOW.
Short Duration (tW < 10s)
When the /SR0 input goes LOW, the internal timer starts
counting. If the /SR0 input goes HIGH before 10s has
elapsed, the timer stops counting and resets and no
changes occur on the outputs.
Long Duration (tW > 10s)
When the /SR0 input goes LOW, the internal timer starts
counting. If the /SR0 input stays LOW for at least 10s, the
RST output is enabled and pulled LOW. The output RST
is held LOW for tREC, 530ms, as soon as the reset time
of 10s is met, regardless of the state of the /SR0 pin.
When the /SR0 input has returned HIGH and tREC has
expired, the internal timer resets and awaits the next
RESET event.
Zero-Second Test Mode
/RST1 goes LOW immediately after /SR0 goes LOW.
N=7.5s
tREC=530ms
Short-Duration,
Normal Operation
/RST1 never goes LOW because
/SR0 LOW duration does not meet
requirement: Reset Time N=10s
Long-Duration,
Normal Operation
/RST1 goes LOW because
/SR0 LOW duration exceeds
requirement: Reset Time N=10s
Zero-Second Factory-Test Mode
/RST1 goes LOW immediately
after /SR0 goes LOW
/SR0
RST1
/SR0
RST1
/SR0
RST1
Figure 3.
Reset Timing Waveforms
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