hbwhelp@micrel.com or (408) 955-1690 Wide MUX The mor" />
參數(shù)資料
型號(hào): FSUSB63UMX
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 10/11頁(yè)
文件大小: 0K
描述: IC USB 2.0 SW & MUX 3:1 12-UMLP
標(biāo)準(zhǔn)包裝: 5,000
功能: USB 開關(guān)
電路: 3:1
導(dǎo)通狀態(tài)電阻: 6 歐姆
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 2.7 V ~ 4.4 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 12-UFQFN
供應(yīng)商設(shè)備封裝: 12-UMLP(1.8x1.8)
包裝: 帶卷 (TR)
Micrel, Inc.
SY87724L
March 2008
8
M9999-032608-B
hbwhelp@micrel.com or (408) 955-1690
Wide MUX
The more typical case will be to convert 8 or 10 bit wide
parallel data words into a serial bit stream. Because the
worst case parallel input rate is on the order of 250 to 340
Mega-transfers per second, single-ended parallel inputs
are used.
This scenario is much like the narrow MUX case, except
now MPINCK+ clocks slower, for 8- or 10-bit parallel
words.
Figure 4. Wide MUX
Note that the input data indication is now single ended,
and that completely different input pins are used, as
compared to the 4 or 5 bit case.
The following table summarizes the available bit widths.
The right column shows the parallel input bits, such as
they will appear in the serial output stream.
Width
Sequence
4
MPF0±, MPF1±, MPF2±, MPF3±
5
MPF0±, MPF1±, MPF2±, MPF3±, MPF4±
8
MP5, MP6, MP7, MP8, MP0, MP1, MP2, MP3
10
MP5, MP6, MP7, MP8, MP9, MP0, MP1, MP2, MP3,
MP4
Table 4. Output Pins for Different Width MUX
Loopback
To ease system design, the SY87724L MDM has the
capability to loop parallel data in, through the MUX, into
the demux, and back to parallel data out. This permits
system check-out through to the individual MDM device.
Note that, for a full check-out, some form of loopback
further down the serial stream is required.
Loopback is incorporated into MDM by modifying the serial
clock, data, and sync inputs to the demux stage.
During loopback, the source of serial information for the
demux
is
changed.
The
MSOUT±,
MTXCLK±
and
MSYNOUT± are internally muxed to the DSIN±, DCKIN±,
and
DFMIN±
nodes
of
the
demux
section.
The
MSYNOUT± signal has the same characteristics as the
DFMIN logic expects.
This exercises the internal data path, both MUX and
demux, for MDM, and also the control logic. The parallel
data presented to the parallel inputs will appear, some
small but unspecified time later, at the parallel outputs.
Figure 5. Loopback Function
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