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參數(shù)資料
| 型號(hào)： | FSUSB20BQX |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大小： | 0K |
| 描述： | IC USB SWITCH DUAL 2X1 14DQFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 功能： | USB 開關(guān) |
| 電路： | 2 x 2:1 |
| 導(dǎo)通狀態(tài)電阻： | 6.5 歐姆 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 14-DQFN |
| 包裝： | 帶卷 (TR) |
Micrel, Inc.
SY54023R
March 2008
6
M9999-033108-A
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
VCCO = 1.14V to 1.26V RL = 50 to VCCO,
VCCO = 1.7V to 1.9V, RL = 50 to VCCO or 100 across the outputs,
VCC = 2.375V to 2.625V. TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
NRZ Data
3.2
Gbps
fMAX
Maximum Frequency
VOUT > 200mV
Clock
2.5
GHz
VIN: 100mV-200mV, Note 6, Figure 1a
250
350
500
ps
VIN: >200mV, Note 6, Figure 1a
200
300
400
ps
tPD
Propagation Delay
IN-to-Q
SEL-to-Q
Figure 1a
90
350
ps
Input-to-Input Skew
Note 6
5
20
ps
Output-to-Output skew
Note 7
3
15
ps
tSkew
Part-to-Part Skew
Note 8
75
ps
Data
Random Jitter
Note 9
1
psRMS
Deterministic Jitter
Note 10
10
psPP
Clock
Cycle-to-Cycle Jitter
Note 11
1
psRMS
Total Jitter
Note 12
10
psPP
tJitter
Crosstalk Induced Jitter
(Adjacent Channel)
Note 13
0.7
psPP
tR tF
Output Rise/Fall Times
(20% to 80%)
At full output swing.
30
60
95
ps
Duty Cycle
Differential I/O
47
53
%
Notes:
6.
Input-to-Input skew is the difference in time between both inputs, measured at the same output, for the same temperature, voltage and
transition.
7.
Output-to-Output skew is the difference in time between both outputs, receiving data from the same input, for the same temperature, voltage
and transition.
8.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs. VIN >200mV with input t
r/tf ≤300ps (20% to 80%).
9.
Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX.
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23–1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 10
12 output edges will deviate by
more than the specified peak-to-peak jitter value.
13. Crosstalk induced jitter is defined as the added jitter that results from signals applied to the adjacent channel. It is measured at the output while
applying a similar, differential clock frequency to both inputs that is asynchronous with respect to each other.
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