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參數(shù)資料
| 型號(hào)： | FSTJ9055D3 |
| 廠商： | INTERSIL CORP |
| 元件分類： | JFETs |
| 英文描述： | Radiation Hardened, SEGR Resistant P-Channel Power MOSFETs |
| 中文描述： | 62 A, 60 V, 0.023 ohm, P-CHANNEL, Si, POWER, MOSFET, TO-254AA |
| 文件頁(yè)數(shù)： | 8/8頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | FSTJ9055D3 |
8
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
ASIA
Intersil Ltd.
8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
FSTJ9055D, FSTJ9055R
TO-254AA
3 LEAD JEDEC TO-254AA HERMETIC METAL PACKAGE
D
L
Q
H
1
e
e
1
J
1
A
1
A
E
P
b
0.065 R MAX.
TYP.
1
2
3
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.249
0.260
6.33
6.60
-
A
1
b
0.040
0.050
1.02
1.27
-
0.035
0.045
0.89
1.14
2, 3
D
0.790
0.800
20.07
20.32
-
E
0.535
0.545
13.59
13.84
-
e
0.150 TYP
3.81 TYP
4
e
1
H
1
J
1
L
0.300 BSC
7.62 BSC
4
0.245
0.265
6.23
6.73
-
0.140
0.160
3.56
4.06
4
0.520
0.560
13.21
14.22
-
P
0.139
0.149
3.54
3.78
-
Q
0.110
0.130
2.80
3.30
-
NOTES:
1. These dimensions are within allowable dimensions of Rev. A of
JEDEC outline TO-254AA dated 11-86.
2. Add typically 0.002 inches (0.05mm) for solder coating.
3. Lead dimension (without solder).
4. Positionofleadtobemeasured0.250inches(6.35mm)frombottom
of dimension D.
5. Die to base BeO isolated, terminals to case ceramic isolated.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
WARNING!
BERYLLIA WARNING PER MIL-S-19500
Packages containing beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical operation
which will produce dust containing any beryllium compound. Packages containing any beryllium compound shall not be
subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its’ compounds.
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