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參數(shù)資料
型號: FSSD06BQX
廠商: Fairchild Semiconductor
文件頁數(shù): 13/14頁
文件大?。?/td> 0K
描述: IC MUX SD/SDIO/MMC 2PORT 24-MLP
標準包裝: 1
類型: 多路復用器
應用: 手機,數(shù)碼相機,媒體播放器
安裝類型: 表面貼裝
封裝/外殼: 24-MLP
供應商設備封裝: 24-MLP(5x5)
包裝: 標準包裝
產(chǎn)品目錄頁面: 1219 (CN2011-ZH PDF)
其它名稱: FSSD06BQXDKR
2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSSD06 Rev. 1.0.5
8
FSSD06
SD/SDIO
and
MMC
Two-Port
Multiplexer
AC Electrical Characteristics at 2.7V VDDH
All typical values are for VDDH=2.7V at 25°C unless otherwise specified.
Symbol
Parameter
VDDC1 /
VDDC2 (V)
Conditions
TA=- 40°C to +85°C
Unit
Min.
Typ.
Max.
tON1
Turn-On Time
S, /OE to CMD, DAT[3:0]
2.7 to 3.6
VSW=0V, RL=1k, CL=30pF
See Figure 7, Figure 8
8
17
ns
tOFF1
Turn-Off Time
S, /OE to CMD, DAT[3:0]
2.7 to 3.6
VSW=0V, RL=1k, CL=30pF
See Figure 7, Figure 8
6
13
ns
tPD
Switch Propagation
Delay
(11)
2.7 to 3.6 See Figure 9
1
ns
tSKEW
Switch Skew
(12)
CMD, DAT[3:0]
2.7 to 3.6 RL=1k, CL=30pF
1.5
ns
tON2
Turn-On Time
S, /OE to 1CLK, 2CLK
2.7 to 3.6
VSW=0V, RL=1k, CL=30pF
See Figure 7, Figure 8
15
25
ns
tOFF2
Turn-Off Time
S, /OE to 1CLK, 2CLK
2.7 to 3.6
VSW=0V, RL=1k, CL=30pF
See Figure 7, Figure 8
10
25
ns
tPDCLK
Clock Propagation Delay
2.7 to 3.6
RL=1k, CL=30pF
See Figure 11
1.5
3.0
ns
OIRR
Off Isolation
(11)
2.7 to 3.6
f=10MHz, RT=50, CL=30pF
See Figure 12
-60
dB
Xtalk
Non-Adjacent Channel
Crosstalk
(11)
2.7 to 3.6
f=10MHz, RT=50, CL=30pF
See Figure 13
-60
dB
ftoggle
Clock Frequency
(11)
2.7 to 3.6 CL=30pF
120
MHz
Notes:
11. Guaranteed by characterization, not production tested.
12. Skew is determined by |TPLH - TPHL | for worst-case temperature and VDDX.
Capacitance
Symbol
Parameter
Conditions
TA=- 40°C to +85°C
Unit
Min.
Typ.
Max.
CIN (S, /OE, CLK)
Control and CLK Pin Input
Capacitance
VDDH=0V
2.5
pF
CON
Common Port On Capacitance
(CDAT[3:0], CMD)
VDDH=1.8V,VDDC1=VDDC2=2.7V,
V/OE=0V, Vbias=0V, f=1MHz
See Figure 15
9.0
COFF
Input Source Off Capacitance
VDDH=1.8V,VDDC1=VDDLH2=2.7V,
V/OE=3.3V, Vbias=0V, f=1MHz
See Figure 14
4.0
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