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參數(shù)資料
| 型號(hào)： | FSHDMI08MTD |
| 廠商： | Fairchild Semiconductor |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC HDMI SWITCH DDC/CEC 56-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 34 |
| 功能： | 開(kāi)關(guān)，DVI/HDMI |
| 電路： | 3 x 2:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
Micrel, Inc.
SY54017R
March 2008
7
M9999-033108-A
hbwhelp@micrel.com or (408) 955-1690
Functional Description
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
output when there is no input signal present, or when
the amplitude of the input signal drops sufficiently
below
100mVPK
(200mVPP),
typically
30mVPK.
Maximum frequency of the SY54017R is limited by
the FSI function.
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing, the FSI function will eliminate a
metastable condition and guarantee a stable output.
No ringing and no undetermined state will occur at the
output under these conditions.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal close to the FSI threshold. Due
to the FSI function, the propagation delay will depend
on rise and fall time of the input signal and on its
amplitude. Refer to “Typical Characteristics” for
detailed information
Interface Applications
For Input Interface Applications, see Figures 4a-f and
for CML Output Termination, see Figures 5a-d.
CML Output Termination with VCCO 1.2V
For VCCO of 1.2V, Figure 5a, terminate the output
with 50
-to-1.2V, DC-coupled, not 100 differentially
across the outputs.
If AC-coupling is used, Figure 5d, terminate into 50
to 1.2V before the coupling capacitor and then
connect to a high value resistor to a reference
voltage.
Do not AC couple with internally terminated receiver.
For example, 50
ANY-IN input. AC-coupling will
offset the output voltage by 200mV and this offset
voltage will be too low for proper driver operation.
CML Output Termination with VCCO 1.8V
For VCCO of 1.8V, Figure 5a and Figure b, terminate
with either 50
-to-1.8V or 100 differentially across
the outputs. AC- or DC-coupling is fine.
Input AC-Coupling
The SY54017R input can accept AC-coupling from
any driver. Bypass VT with a 0.1F low ESR capacitor
to VCC as shown in Figures 4c and 4d. VT has an
internal high impedance resistor divider as shown in
Figure 2a, to provide a bias voltage for AC-coupling.
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