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參數(shù)資料
| 型號： | FSHDMI04MTDX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 0K |
| 描述： | IC SWITCH HDMI WIDE BAND 48TSSOP |
| 標準包裝： | 1 |
| 功能： | 開關(guān)，DVI/HDMI |
| 電路： | 3 x 2:1 |
| 導(dǎo)通狀態(tài)電阻： | 19 歐姆 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | FSHDMI04MTDXDKR |
Micrel, Inc.
SY54017AR
May 2008
6
M9999-053008-B
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
VCCO = 1.14V to 1.26V RL = 50 to VCCO, VCCO = 1.7V to 1.9V, RL = 50 to VCCO or 100 across the outputs,
VCC = 2.375V to 2.625V. TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
NRZ Data
3.2
Gbps
fMAX
Maximum Frequency
VOUT > 200mV
Clock
3.2
GHz
Figure 1a
150
225
310
ps
tPD
Propagation Delay
IN-to-Q
SEL-to-Q
Figure 1a
90
200
350
ps
Input-to-Input Skew
Note 6
5
20
ps
tSkew
Part-to-Part Skew
Note 7
75
ps
Data
Random Jitter
Note 8
1
psRMS
Deterministic Jitter
Note 9
10
psPP
Clock
Cycle-to-Cycle Jitter
Note 10
1
psRMS
Total Jitter
Note 11
10
psPP
tJitter
Crosstalk Induced Jitter
(Adjacent Channel)
Note 12
0.7
psPP
tR tF
Output Rise/Fall Times
(20% to 80%)
At full output swing.
30
60
95
ps
Duty Cycle
Differential I/O
47
53
%
Notes:
6.
Input-to-Input skew is the difference in time between both inputs and the output for the same temperature, voltage and transition.
7.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
8.
Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX.
9.
Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2
23–1 PRBS pattern.
10. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
11. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 10
12 output edges will deviate by
more than the specified peak-to-peak jitter value.
12. Crosstalk induced jitter is defined as the added jitter that results from signals applied to the adjacent channel. It is measured at the output while
applying a similar, differential clock frequencies that are asynchronous with respect to each other at the adjacent input.
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