參數(shù)資料
型號: FSDH0170RNB
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: Green Mode Fairchild Power Switch (FPSTM)
中文描述: 4 A SWITCHING REGULATOR, 108 kHz SWITCHING FREQ-MAX, PDIP8
封裝: MS-001BA, DIP-8
文件頁數(shù): 9/19頁
文件大?。?/td> 608K
代理商: FSDH0170RNB
9
www.fairchildsemi.com
FSDH0170RNB/FSDH0270RNB/FSDH0370RNB Rev. 1.0.2
F
Functional Description
1. Startup:
In previous generations of Fairchild Power
Switches (FPS) the Vstr pin required an external
resistor to the DC input voltage line. In this generation
the startup resistor is replaced by an internal high
voltage current source and a switch that shuts off 10ms
after the supply voltage, Vcc, goes above 12V. The
source turns back on if Vcc drops below 8V.
Figure 4. High Voltage Current Source
2. Feedback Control:
The 700V FPS series employs
current mode control, as shown in Figure 5. An
optocoupler (such as the H11A817A) and shunt
regulator (such as the KA431) are typically used to
implement the feedback network. Comparing the
feedback voltage with the voltage across the Rsense
resistor of Sense FET plus an offset voltage makes it
possible to control the switching duty cycle. When the
KA431 reference pin voltage exceeds the internal
reference voltage of 2.5V, the optocoupler LED current
increases, the feedback voltage Vfb is pulled down and
thereby reduces the duty cycle. This typically happens
when the input voltage increases or the output load
decreases.
Figure 5. Pulse Width Modulation (PWM) Circuit
3. Leading Edge Blanking (LEB):
When the internal
Sense FET is turned on; the primary side capacitance
and secondary side rectifier diode reverse recovery
typically cause a high current spike through the Sense
FET. Excessive voltage across the Rsense resistor
leads to incorrect feedback operation in the current
mode PWM control. To counter this effect, the FPS
employs a Leading Edge Blanking (LEB) circuit. This
circuit inhibits the PWM comparator for a short time
(t
LEB
) after the Sense FET is turned on.
4. Protection Circuits:
The FPS has several protective
functions such as Over Load Protection (OLP), Over
Voltage Protection (OVP), Under Voltage Lock Out
(UVLO), and Thermal Shut Down (TSD). Because these
protection circuits are fully integrated inside the IC
without external components, reliability is improved
without increasing cost. Once a fault condition occurs,
switching is terminated and the Sense FET remains off.
This causes Vcc to fall. When Vcc reaches the UVLO
stop voltage, V
STOP
(typically 8V), the protection is reset
and the internal high voltage current source charges the
Vcc capacitor via the Vstr pin. When Vcc reaches the
UVLO start voltage, V
START
(typically 12V), the FPS
resumes its normal operation. In this manner, the auto-
restart can alternately enable and disable the switching
of the power Sense FET until the fault condition is
eliminated.
4.1 Over Load Protection (OLP):
Overload is defined
as the load current exceeding a pre-set level due to an
unexpected event. In this situation, the protection circuit
should be activated in order to protect the SMPS.
However, even when the SMPS is operating normally,
the Over Load Protection (OLP) circuit can be activated
during the load transition. In order to avoid this undesired
operation, the OLP circuit is designed to be activated
after a specified time to determine whether it is a
transient situation or an overload situation. In
conjunction with the Ipk current limit pin (if used) the
current mode feedback path would limit the current in the
Sense FET when the maximum PWM duty cycle is
attained. If the output consumes more than this
maximum power, the output voltage (Vo) decreases
below its nominal voltage. This reduces the current
through the optocoupler LED, which also reduces the
optocoupler transistor current, thus increasing the
feedback voltage (V
FB
). If V
FB
exceeds 3V, the feedback
input diode is blocked and the 5μA current source
(I
DELAY
) starts to slowly charge Cfb up to Vcc. In this
condition, V
FB
increases until it reaches 6V, when the
switching operation is terminated as shown in Figure 6.
The shutdown delay time is the time required to charge
Cfb from 3V to 6V with 5μA current source.
Vin,dc
Vstr
Vcc
10ms after
Vcc
12V
UVLO off
Vcc<8V
UVLO on
I
STR
J-FET
I
CH
3
OSC
Vcc
Vcc
5uA
0.9mA
V
SD
R
2.5R
Gate
driver
OLP
D1
D2
V
FB
Vfb
431
C
FB
Vo
+
-
V
FB,in
相關PDF資料
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FSDH0270RNB Green Mode Fairchild Power Switch (FPSTM)
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