參數(shù)資料
型號(hào): FSD210B
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: Green Mode Fairchild Power Switch (FPS)
中文描述: 0.365 A SWITCHING REGULATOR, 142 kHz SWITCHING FREQ-MAX, PDIP7
封裝: DIP-7
文件頁(yè)數(shù): 9/18頁(yè)
文件大小: 853K
代理商: FSD210B
FSD210B, FSD200B
9
Functional Description
1. Startup
: At startup, the internal high voltage current
source supplies the internal bias and charges the external
Vcc capacitor as shown in Figure 7. In the case of the
FSD210B, when Vcc reaches 8.7V the device starts
switching and the internal high voltage current source is
disabled. The device is in normal operation provided that
Vcc does not drop below 6.7V. After startup the bias is
supplied from the auxiliary transformer winding. In the case
of FSD200B, An internal high voltage regulator (HV Req.)
located between Vstr pin and Vcc pin regulates the Vcc to be
7V and supplies operating current, thus FSD200B needs no
auxiliary bias winding.
Figure 6. Internal Startup Circuit
Figure 7. Charging Vcc Capacitor through Vstr
Calculating the Vcc capacitor is an important step to design
with the FSD200B/210B. At initial start-up in the both
devices, the maximum value of start operating current
I
START
is about 100uA, which supplies current to UVLO
and Vref Blocks. The charging current I
Vcc
of the Vcc
capacitor is equal to I
STR
- 100uA. After Vcc reaches the
UVLO start voltage only the bias winding supplies Vcc
current to device. When the bias winding voltage is not suffi-
cient, the Vcc level decreases to the UVLO stop voltage. At
this time Vcc oscillates. In order to prevent this oscillation it
is recommended that the Vcc capacitor be chosen to have the
value between 10uF and 47uF.
2. Feedback Control
: The FSD200B/210B are voltage
mode controlled devices as shown in Figure 8. Usually, an
opto-coupler and KA431 type voltage reference are used to
implement the feedback network. The feedback voltage is
compared with an internally generated sawtooth waveform.
This directly controls the duty cycle. When the KA431
reference pin voltage exceeds the internal reference voltage
of 2.5V, the optocoupler LED current increases, the feedback
voltage Vfb is pulled down and it reduces the duty cycle.
This will happen when the input voltage increases or the
output load decreases.
Figure 8. PWM and Feedback Circuit
3. Leading Edge Blanking (LEB)
: At the instant the inter-
nal Sense FET is turned on, the primary side capacitance and
secondary side rectifier diode reverse recovery typically
cause a high current spike through the Sense FET. Excessive
voltage across the Rsense resistor leads to incorrect feedback
operation in the current mode PWM control. To counter this
effect, the FPS employs a leading edge blanking (LEB) cir-
cuit. This circuit inhibits the PWM comparator for a short
time (t
LEB
) after the Sense FET is turned on.
Vin,dc
Vstr
Vcc
HV
Reg.
Vin,dc
Vstr
Vcc
7V
I
STR
FSD210B
FSD200B
8.7V/
6.7V
L
H
I
STR
Vin,dc
Vstr
J-FET
UVLO
Vref
I
START
I
VCC
= I
STR
START
I
VCC
= I
-I
START
FSD2xx
Vcc
V
START
V
STOP
t
Vcc
Vcc must not drop
below V
STOP
Bias winding
voltage
UVLO
I
STR
4
OSC
Vcc
Vref
5uA
0.25mA
V
SD
R
Gate
driver
OLP
Vfb
KA431
Cfb
Vo
+
V
FB
-
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