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參數(shù)資料
| 型號(hào)： | FSCQ1565RPSYDTU |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Green Mode Fairchild Power Switch (FPS) for Quasi-Resonant Switching Converter |
| 中文描述： | 33.2 A SWITCHING REGULATOR, 22 kHz SWITCHING FREQ-MAX, PZFM5 |
| 封裝： | TO-3PF, 7/5 PIN |
| 文件頁數(shù)： | 15/44頁 |
| 文件大?。?/td> | 1204K |
| 代理商： | FSCQ1565RPSYDTU |
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FSCQ-SERIES
15
Once the FSCQ-Series enters into
the
extended quasi-
resonant operation, the first sync signal is ignored. After the
first sync signal is applied, the sync threshold levels are
changed from 4.6V and 2.6V to 3V and 1.8V, respectively,
and the MOSFET turn-on time is synchronized to the second
sync signal. The FSCQ-Series returns to its normal quasi-
resonant operation when the switching frequency reaches
45kHz as the load increases.
Figure 10. Extended Quasi-Resonant Operation Wave-
forms
3. Feedback Control
:
The
FSCQ-Series employs current
mode control, as shown in Figure 11. An opto-coupler (such
as
Fairchild’s
H11A817A) and shunt regulator (such as
Fairchild’s
KA431) are typically used to implement the
feedback network. Comparing the feedback voltage with the
voltage across the Rsense resistor plus an offset voltage
makes it possible to control the switching duty cycle. When
the reference pin voltage of the KA431 exceeds the internal
reference voltage of 2.5V, the H11A817A LED current
increases, pulling down the feedback voltage and reducing
the duty cycle. This event typically happens when the input
voltage is increased or the output load is decreased.
3.1 Pulse-by-
P
ulse Current Limit
: Because current mode
control is employed, the peak current through the
SenseFET
is limited by the inverting input of the PWM
comparator (Vfb*) as shown in Figure 11. The feedback
current (I
FB
) and internal resistors are designed so that the
maximum cathode voltage of diode D
2
is about 2.8V, which
occurs when all I
FB
flows through the internal resistors.
Since D
1
is blocked when the feedback voltage (Vfb)
exceeds 2.8V, the maximum voltage of the cathode of D2 is
clamped at this voltage, thus clamping Vfb*. Therefore, the
peak value of the current through the SenseFET is limited.
3.2 Leading Edge Blanking (LEB)
: At the instant the
internal Sense FET is turned on, there is usually a high
current spike through the Sense FET, caused by the external
resonant capacitor across the MOSFET and secondary-side
rectifier reverse recovery. Excessive voltage across the
R
sense
resistor can lead to incorrect feedback operation in
the current mode PWM control. To counter this effect, the
FSCQ-Series employs a leading edge blanking (LEB)
circuit. This circuit inhibits the PWM comparator for a short
time (T
LEB
) after the Sense FET is turned on.
Figure 11. Pulse Width Modulation (PWM) Circuit
4. Protection Circuits
: The FSCQ-Series has several self-
protective functions such as over load protection (OLP),
abnormal over current protection (AOCP), over voltage
protection (OVP)
,
and thermal shutdown (TSD). OLP and
OVP are auto-restart mode protection
s
, while TSD and
AOCP are latch mode protection
s
. Because these protection
circuits are fully integrated into the IC without external
components, the reliability can be improved without
increasing cost.
-Auto-restart mode protection
: Once the fault condition is
detected, switching is terminated and the SenseFET remains
off. This causes Vcc to fall. When Vcc falls to the under
voltage lockout (UVLO) stop voltage of 9V, the protection is
reset and
the
FSCQ-Series consumes only startup current
(25uA). Then, the Vcc capacitor is charged up, since the
current supplied through the startup resistor is larger than the
current that
the
FPS consumes. When Vcc reaches the start
voltage of 15V, the FSCQ-Series resumes its normal
operation. If the fault condition is not removed, the
SenseFET remains off and Vcc drops to stop voltage again.
In this manner, the auto-restart can alternately enable and
disable the switching of the power SenseFET until the fault
condition is eliminated (see Figure 12).
-Latch mode protection
: Once this protection is triggered,
switching is terminated and the Sense FET remains off until
the AC power line is un-plugged. Then, Vcc continues
charging and discharging between 9V and 15V. The latch is
reset only when Vcc is discharged to 6V by un-plugging the
Vsync
Vds
MOSFET Gate
2V
RO
4.6V
2.6V
3V
1.8V
ON
ON
4
OSC
Vcc
Vref
I
delay
I
FB
V
SD
R
2.5R
Gate
driver
OLP
D1
D2
+
V
fb
*
-
Vfb
KA431
C
B
Vo
H11A817A
R
sense
SenseFET
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