Low EMI Spread Spectrum Clock
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress
Document#: 38-07031 Rev. **
05/04/2001
Page 9 of 13
APPROVED
PRODUCT
FS786/787
Fc = 20 MHz
Fmin =
19.8 MHz
Fmax =
20.2 MHz
Theory of Operation
The FS786/787 devices are Phase Lock Loop (PLL) type clock generators using Direct Digital Synthesis (DDS).
By precisely controlling the bandwidth of the output clock, the FS786/787 products become a Low EMI clock
generator. The theory and detailed operation of these
products will be discussed in the following sections.
EMI
All clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50 %. Because of the 50/50 duty cycle,
digital clocks generate most of their harmonic energy in the
odd harmonics, i.e.; 3
rd
, 5
th
, 7
th
etc. It is possible to reduce the
amount of energy contained in the fundamental and
harmonics by increasing the bandwidth of the fundamental clock frequency. Conventional digital
clocks have a very high Q factor, which means that all of the energy at that frequency is concentrated in a very
narrow bandwidth, consequently, higher energy peaks. Regulatory agencies test electronic equipment by the
amount of peak energy radiated from the equipment. By reducing the peak energy at the fundamental and
harmonic frequencies, the equipment under test is able to satisfy agency requirements for Electro-Magnetic
Interference (EMI). Conventional methods of reducing EMI have been to use shielding, filtering, multi-layer PCB
’
s
etc. The FS786 and 787 use the approach of reducing the peak energy in the clock by increasing the clock
bandwidth, and lowering the Q of the clock.
SSCG
The FS786/787 products use a unique method of modulating the clock over a very narrow bandwidth and
controlled rate of change, both peak to peak and cycle to cycle. The FS78x products take a narrow band digital
reference clock in the range 6 - 82 MHz and produce a clock that sweeps between a controlled start and stop
frequency and precise rate of change. To understand what happens to an SSCG clock, consider that we have a
20 MHz clock with a 50 % duty cycle. From a 20 MHz clock we know the following;
Clock Frequency = Fc = 20 MHz.
Clock Period = Tc = 1/20 MHz=50 ns
Consider that this 20 MHz clock is applied to the Xin input of the FS78x,
either as an externally driven clock or as the result of a parallel resonant
crystal connected to pins 1 and 2 of the FS78x. Also consider that the
products are operating from a 5-volt DC power supply and the loop filter is
set for a total bandwidth spread of 2%. Refer to table 6 on page 6.
From the above parameters, the output clock at FSOUT will be sweeping
symmetrically around a center frequency of 20 MHz.
The minimum and maximum extremes of this clock will be +200 kHz and -
200 kHz. So, we have a clock that is sweeping from 19.8 MHz to 20.2 MHz
and back again. If we were to look at this clock on a spectrum analyzer we
would see the picture in figure 7. Keep in mind that this is a drawing of a
perfect clock with no noise.
Figure 7.
50%
50%
Tc = 50 ns.
20 MHz Unmodulated Clock