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參數(shù)資料
| 型號： | FS7145-01-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN I2C PROGR 16-SOIC |
| 標(biāo)準包裝： | 3,000 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 帶卷 (TR) |
FS7140, FS7145
http://onsemi.com
5
Parameter
Units
Max
Typ
Min
Conditions/Description
Symbol
CLOCK OUTPUTS, CMOS MODE (CLKN, CLKP)
Lowlevel output sink current
IOL
VO = 0.4 V
35
mA
CLOCK OUTPUTS, PECL MODE (CLKN, CLKP)
IPRG bias voltage
VIPRG
VIPRG will be clamped to this level
when a resistor is connected from
VDD to IPRG
VDD/3
V
IPRG bias current
IIPRG
IIPRG (VVDD VIPRG) / RSET
3.5
mA
Sink current to IPRG current ratio
13
Tristate output current
IZ
10
mA
1. Unless otherwise stated, VDD = 3.3 V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characteriza-
tion data are ± 3s from typical. Negative currents indicate flows out of the device.
Table 5. AC TIMING SPECIFICATIONS (Note 2)
Parameter
Symbol
Conditions/Description
Min
Typ
Max
Units
OVERALL
Output frequency*
fo(max)
CMOS outputs
0
150
MHz
PECL outputs
0
300
VCO frequency*
fVCO
40
400
MHz
CMOS mode rise time*
tr
CL = 7 pF
1
ns
CMOS mode fall time*
tf
CL = 7 pF
1
ns
PECL mode rise time*
tr
CL = 7 pF; RL = 65 ohm
1
ns
PECL mode fall time*
tf
CL = 7 pF; RL = 65 ohm
1
ns
REFERENCE FREQUENCY INPUT (REF)
Input frequency
FREF
80
MHz
Reference high time
tREHF
3
ns
Reference low time
tREFL
3
ns
SYNC CONTROL INPUT (SYNC)
Sync high time
tSYNCH
For orderly CLK stop/start
3
TCLK
Sync low time
tSYNCL
For orderly CLK stop/start
3
CLOCK OUTPUT (CLKN, CLKP)
Duty cycle (CMOS mode)*
Measured at 1.4 V
50
%
Duty cycle (PECL mode)*
Measured at zero crossings of
(VCLKP VCLKN)
50
%
Jitter, long term (sy(t))*
tj(LT)
For valid programming solutions. Long-term (or cumulative) jitter specified is
RMS position error of any edge compared with an ideal clock generated from
the same reference frequency. It is measured with a time interval analyzer us-
ing a 500 microsecond window, using statistics gathered over 1000 samples.
ps
FREF/NREF > 1000 kHz
25
ps
FREF/NREF ^ 500 kHz
50
ps
FREF/NREF ^ 250 kHz
100
ps
FREF/NREF ^ 125 kHz
190
ps
FREF/NREF ^ 62.5 kHz
240
ps
FREF/NREF ^ 31.5 kHz
300
ps
Jitter, period (peakpeak)*
tj(DP)
40 MHz < VCO frequency < 100 MHz
75
ps
VCO frequency > 100 MHz
50
ps
2. Unless otherwise stated, VDD = 3.3 V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization
data are ± 3s from typical.
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