參數(shù)資料
型號(hào)： FS451
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： i-Net TV Interface Video Processor
中文描述： 一至網(wǎng)絡(luò)電視接口視頻處理器
文件頁(yè)數(shù)： 30/60頁(yè)
文件大小： 266K
代理商： FS451
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
JUNE, 2000, VERSION 1.2
30
COPYRIGHT
ó
1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
H
C
Load
FLT_HSTART
FLT_VSTART
S
C
TV_HSTART
TV_HEND
TV_VEND
TV_FIELD
TV_VSTART
TV Pixel
Counter
TV Field
Counter
TV Line
Counter
Aux Pixel
Counter
Aux Field
Counter
Aux Line
Counter
S
C
AUX_HREF
FLT_FIELD
AUX_VREF
Figure 8: CCIR 656 Timing Block Diagram
The TV and Auxiliary Pixel/Line/Field Counters are freewheeling counters that are only loaded/reloaded
during an error condition. If the value of the TV Pixel/Line/Field Counters are within 4 TV pixels of the ideal
values during a Frame Start, no adjustment to the freewheeling counters are made. However, if the values
exceeds 4 pixels (150 nsec) the ideal values, the TV Pixel/Line/Field Counters are reloaded and the TV
Counter Acquisition Flag is set.
When the TV Pixel/Line/Field Counters are reloaded, the Auxiliary Pixel/Line/Field Counters are also
reloaded. However, their load values are offset from the TV counter by the Auxiliary Pixel, Line, and Field
Offset values stored in its I2C registers (APO, ALO, and AFO). From these counters the Auxiliary
Horizontal and Vertical Syncs are formed. This feature allows a user to program advance timing signals to
compensate for external hardware processing latency when doing a mix/overlay with FS450’s CCIR 656
input and output.
The FIFO Latency register delays the Frame Start occurrence by 4x its value in 27MHz clock cycles. This
delays the output 656 timing with respect to the input VGA timing and allows the FS450’s FIFO to fill
appropriately before a FIFO read is initiated.
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