MB91360G Series
89
5.
DMA CONTROLLER
(
DMAC
)
The DMAC module is used to implement direct memory access (DMA) transfer in FR50 series devices.
In a DMA transfer controlled by this module, various types of data can be transferred at high speed without
involving the CPU, thus increasing system performance.
(1) Hardware Configuration
The following are the main components of the DMAC module :
Five independent DMA channels
5-channel independent access control circuit
32-bit address registers (Reload can be specified : Two registers for each channel.)
16-bit transfer count registers (Reload can be specified : One register for each channel.)
4-bit block count registers (One register for each channel)
External transfer request input pins DREQ0, DREQ1, and DREQ2 (only channels 0, 1, and 2)
External transfer request acceptance output pins DACK0, DACK1, and DACK2 (only channels 0, 1, and 2)
DMA termination output pins DEOP0, DEOP1, and DEOP2 (only channels 0, 1, and 2)
Two-cycle transfer
(2) Main Functions
The following are the main functions of data transfer performed by the module :
Independent data transfer in multiple channels is enabled (5 channels) .
a : Priority (channel 0
>
channel 1
>
channel 2
>
channel 3
>
channel 4)
b : Priority can be alternated between channel 0 and channel 1.
c : DMAC start cause
External-only pin input (edge detection/level detection channels 0 to 2 only)
Internal peripheral request (interrupt request is shared, including external interrupts)
Software request (register write)
d : Transfer mode
Demand transfer, burst transfer, step transfer, block transfer
Addressing mode 32-bit full address specification (increase, decrease, fixed)
(An address increment/decrement size of
255 to
+
255 can be specified.)
Data types of byte, halfword, and word lengths
Single-shot/reload selectable