參數(shù)資料
型號： FPD87392BXBVQ
廠商： National Semiconductor Corporation
英文描述： +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA)
中文描述： 3.3 TFT - LCD的雙LVDS輸入定時控制器/雙⑩輸出區(qū)特別職務(wù)隊的TFT - LCD顯示器和筆記本電腦（SXGA / SXGA / UXGA）下
文件頁數(shù)： 3/30頁
文件大?。?/td> 1980K
代理商： FPD87392BXBVQ
Block Diagram
Functional Description
DUAL FPD-LINK RECEIVERS
The LVDS based FPD-Link Receivers inputs video data and
control timing through 8 pairs of LVDS channels plus 2 pairs
of LVDS clocks to provide 24-bit color or use only 6 pairs of
LVDS channels plus 2 LVDS clocks to provide 18-bit color.
The video data is converted to a parallel data stream and
routed to the 8-6 bit translator.
SPREAD SPECTRUM SUPPORT
The FPD-Link receiver supports graphics controllers with
Spread Spectrum interfaces for reducing EMI. The Spread
Spectrum methods supported are Center and Down Spread.
A maximum of 2% total is supported at a frequency modu-
lation of 100kHz maximum.
8-6 BIT TRANSLATOR
8-bit data is reduced to a 6-bit data path via a time multi-
plexed dithering technique or simple truncation of the LSBs.
This function is enabled via the input control pins.
DATAPATH BLOCK AND RSDS TRANSMITTER
6(8)-bit video data (RGB) is input to the Datapath Block
supports up to an 85 MHz dual pixel rate. The data is
delayed to align the Column Driver Start Pulse (STH) with
the Column Driver data. The dual data bus (RSR[3:0]P/N,
RSG[3:0]P/N, RSB[3:0]P/N) outputs at a 170 MHz rate on 24
differential output channels. The clock is output on the
(Front, Back) RSCKP/N differential pairs. The RSDS Column
Drivers latch data on both positive and negative edges of the
clock. The swap function provides flexible RSDS data output
mappings for either Top or Bottom mount. The RSDS output
setup/hold
timings
are
also
RSKEW[2:0] input pins.
adjustable
through
the
TIMING CONTROL FUNCTION
The Timing Control function generates control to Column
Drivers, Row Drivers, and power supply. The GPOs (General
Purpose Outputs) provide for CD latch pulse, REV, and Row
Driver control generation. The General Purpose Outputs
allow the user to generate control anywhere within the frame
data. Standard Row Driver interface or Custom Row Driver
interfaces can be implemented with the GPOs (General
Purpose Outputs).
RSDS OUTPUT VOLTAGE CONTROL
The RSDS output voltage swing is controlled through an
external load resistor connected to the RPI pin. The RSDS
output signal levels can be adjusted to suit the particular
application. This is dependent on overall LCD module design
characteristics such as trace impedance, termination, etc.
The RSDS output voltage is inversely related to the RPI
value. Lower RPI values will increase the RSDS output
voltage swing and consequently overall power consumption
will also increase.
20104328
FIGURE 2. Block Diagram
F
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