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參數(shù)資料
| 型號： | FOD2200V |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 光電耦合器 |
| 英文描述： | LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS |
| 中文描述： | 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER |
| 封裝： | DIP-8 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 210K |
| 代理商： | FOD2200V |
7/7/04
Page 5 of 14
2004 Fairchild Semiconductor Corporation
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
1. The V
CC
supply to each optoisolator must be bypassed by a 0.1μF capacitor or larger. This can be either a ceramic or solid
tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package V
CC
and GND pins of each device.
2. t
PLH
- Propagation delay is measured from the 50% level on the LOW to HIGH transition of the input current pulse to the
1.3V level on the LOW to HIGH transition of the output voltage pulse.
3. t
PHL
- Propagation delay is measured from the 50% level on the HIGH to LOW transition of the input current pulse to the 1.3V
level on the HIGH to LOW transition of the output voltage pulse.
4. When the peaking capacitor is omitted, propagation delay times may increase by 100 ns.
5. t
r
- Rise time is measured from the 10% to the 90% levels on the LOW to HIGH transition of the output pulse.
6. t
f
- Fall time is measured from the 90% to the 10% levels on the HIGH to LOW transition of the output pulse.
7. CM
H
- The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the high state (i.e.,
V
OUT
> 2.0 V).
8. CM
L
- The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low state (i.e.,
V
OUT
< 0.8 V).
9. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
10. Duration of output short circuit time should not exceed 10 ms.
NOTES
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