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參數(shù)資料
| 型號： | FOD2200SDV |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 光電耦合器 |
| 英文描述： | LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS |
| 中文描述： | 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER |
| 封裝： | SURFACE MOUNT, DIP-8 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 210K |
| 代理商： | FOD2200SDV |
7/7/04
Page 3 of 14
2004 Fairchild Semiconductor Corporation
LOW INPUT CURRENT
LOGIC GATE OPTOCOUPLERS
FOD2200
** Typical values at T
A
= 25°C, V
CC
= 5V, I
F(ON)
= 3 mA unless otherwise specified.
ELECTRICAL CHARACTERISTICS
V
EH
= 2V to 20V, V
= 0V to 0.8V, I
(T
A
= 0°C to +85°C, V
= 0 mA to 0.1 mA Unless otherwise specified.) See Note 1.
CC
= 4.5V to 20V, I
F(ON)
= 1.6mA to 5mA,
F(OFF)
INDIVIDUAL COMPONENT CHARACTERISTICS
Parameter
EMITTER
Input Forward Voltage
Input Reverse Breakdown Voltage
Input Capacitance
Input Diode Temperature Coefficient
DETECTOR
Test Conditions
Symbol
Min
Typ**
Max
Unit
(I
F
T
= 10 μA)
= 5 mA)
=25°C
V
F
1.75
1.7
V
A
1.40
(I
R
B
C
VF/
VR
5.0
V
pF
(Pins 2 & 3) (V
F
= 0, f = 1 MHz)
(I
F
= 5 mA)
IN
60
-1.4
TA
mV/°C
High Level Supply Current
(I
F
= 5 mA)
(I
O
= Open, V
E
= Don’t care)
V
V
V
V
CC
= 5.5V
= 20V
= 5.5V
= 20V
= 0.4 V
= 2.7 V
= 5.5 V
= 20 V
I
CCH
3.5
4.0
4.4
5.2
-0.1
4.5
6.0
6.0
7.5
-0.32
20
100
250
mA
CC
Low Level Supply Current
(I
F
= 0 )
(I
O
= Open, V
E
= Don’t care)
CC
I
CCL
mA
CC
V
E
V
E
V
E
V
Low Level Enable Current
I
EL
mA
High Level Enable Current
I
EH
μA
E
0.005
High Level Enable Voltage
Low Level Enable Voltage
V
V
EH
2.0
V
V
EL
0.8
SWITCHING CHARACTERISTICS
V
CC
= 4.5 to 20V Unless otherwise specified.)
(T
A
= 0°C to +85°C, I
F(ON)
= 1.6mA to 5mA, I
F(OFF)
= 0 to 0.1 mA,
AC Characteristics
Test Conditions Symbol
Min
Typ**
Max
Unit
Propagation Delay Time
to Output High Level
(Note 2, 4)
T
PLH
120
300
ns
(Fig. 1) With Peaking Capacitor
Propagation Delay Time
to Output Low Level
Output Rise Time (10-90%)
Output Fall Time (90-10%)
Enable Propagation Delay Time
to Output High Level
Enable Propagation Delay Time
to Output Low Level
Disable Propagation Delay Time from Output High Level (Fig. 2)
Disable Propagation Delay Time from Output Low Level (Fig. 2)
Common Mode
Transient Immunity
(at Output High Level)
Common Mode
Transient Immunity
(at Output Low Level)
(Note 3, 4)
T
PHL
180
300
ns
(Fig. 1) With Peaking Capacitor
(Note 5) (Fig. 1)
(Note 6) (Fig. 1)
t
t
r
80
25
ns
ns
f
(Fig. 2)
t
PZH
40
ns
(Fig. 2)
t
PZL
50
ns
T
T
PHZ
95
80
ns
ns
PLZ
(T
A
=25°C)
(I
F
= 1.6 mA, V
V
CC
OH
(Min.) = 2.0 V)
= 5V (Note 7)(Fig. 3)
(T
= 0 mA, V
OL
(Max.) = 0.8 V)
V
CC
= 5V (Note 8)(Fig. 3)
|V
CM
| = 50 V
|CM
H
|
1000
V/μs
A
=25°C)
(I
F
|V
CM
| = 50 V
|CM
L
|
1000
V/μs
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