參數(shù)資料
型號: foa3251p
廠商: SIEMENS AG
英文描述: Clock & Data Recovery Chip CDR 2.5 - 2.66 Gbit/s, 3.3 to 5.0 V(時鐘及數(shù)據(jù)恢復(fù)芯片)
中文描述: 時鐘
文件頁數(shù): 1/2頁
文件大小: 66K
代理商: FOA3251P
tracts the clock signal from an in-
coming bitstream up to 2.66 Gbit/s.
http://www.infineon.com/fast!logic
Product Brief
FOA3251B1
C
lock &
D
ata
R
ecovery Chip
CDR
2.5 - 2.66 Gbit/s, 3.3 to 5.0 V
Semiconductor Solutions for
High Speed Communication and
Fiber Optic Applications
Features
I
Data rate from 2.488 up to
2.663 Gbit/s by change
of ref clock
I
Jitter performance compliant to
ITU-T G958 and GR-253-Core
requirements
I
Supply voltage: 3.0 V - 5.0 V
I
Supply current: 200 mA
I
Input sensitivity: < 10 mV
pp
at BER = 10
-12
I
Adjustable data/clock- phase
shift by programmable delay line
I
Loss of lock indication
I
External active loop filter for
optimization of jitter performance
I
Good power supply rejection
due to external
V
ref
I
Continuous output clock signal
at loss of signal condition due to
ext. ref. clock (typical application
Datacom/Serdes)
I
Reference clock: 19.44 MHz
I
Internal low phase noise
LC-Oscillator
I
LOS- and LOL detection
I
Statistical LOS for white
noise detection (optimized for
APD applications)
I
Level detection
(can be disabled and adjusted)
I
Automatic eye adjustment due
to special phase detector design
I
Package P-LQFP-48-1 or chip
Typical Applications
I
Fiber optics telecom and data
communication systems
I
SDH/SONET, Fiber Channel,
Gigabit Ethernet
Main Advantages
I
Optimized for high input
sensitivity due to novel PLL
structure and low noise limiting
amplifier
I
Extended power supply range
Packing
Type
FOA3251B1
FOA3252B1
Ordering Code
Q67001-H4145
Q67000-H4160
Package
P-LQFP-48-1
Chip/bare die
The FOA3251/52B1 is a high per-
formance monolithic integrated
C
lock &
D
ata
R
ecovery (
CDR
)
device applicable for optical com-
munication systems such as
SDH STM-16 and SONET OC-48.
The circuit recovers data and ex-
Due to its self - tuning internal
LC-VCO, the
CDR
operates from
2.5 - 2.66 Gbit/s automatically.
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