4
.
Output Current
I
O(ERR)
FB Forced to V
OUT
- 3%
-
1
-
mA
Input Bias Current
I
FB
-
5
100
nA
Maximum Output Voltage
V
COMP(MAX)
FB Forced to V
OUT
- 3%
-
3.0
-
V
Output Disable Threshold
V
COMP(OFF)
560
720
800
mV
FB Low Foldback Threshold
V
FB(LOW)
375
425
500
mV
-3dB Bandwidth
BW
ERR
COMP = Open
-
500
-
kHz
CURRENT SENSE
Threshold Voltage
V
CS(TH)
CS+ = VCC, FB Forced to V
OUT
- 3%
0.8
≤
COMP
≤
1V
69
79
89
mV
-
0
15
mV
Current Limit Foldback Voltage
V
CS(FOLD)
FB
≤
375mV
37
47
58
mV
V
COMP
/
V
CS
n
i
1 V
≤
V
COMP
≤ 3
V
-
25
-
V/V
Input Bias Current
I
CS+
, I
CS-
CS+ = CS- = VCC
-
0.5
5.0
μ
A
Response Time
t
CS
CS+ - (CS-)
≥
89mV to PWM Going Low
-
50
-
ns
POWER GOOD COMPARATOR
Undervoltage Threshold
V
PWRGD(UV)
Percent of Nominal Output
76
82
88
%
Overvoltage Threshold
V
PWRGD(OV)
Percent of Nominal Output
V
OL(PWRGD)
I
PWRGD(SINK)
= 100
μ
A
114
124
134
%
Output Voltage Low
-
30
200
mV
Response Time
-
200
-
ns
PWM OUTPUTS
Output Voltage Low
V
OL(PWM)
I
PWM(SINK)
= 400
μ
A
I
PWM(SOURCE)
= 400
μ
A
-
100
500
mV
Output Voltage High
V
OH(PWM)
4.5
5.0
5.5
V
Output Current
I
PWM
0.4
1
-
mA
Duty Cycle Limit, by Design
D
MAX
Per Phase, Relative to f
CT
-
-
50
%
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
V
CC
CORE
(VDC)
VID25mV
VID3
VID2
VID1
VID0
0
0
1
0
0
1.050
1
0
1
0
0
1.075
0
0
0
1
1
1.100
1
0
0
1
1
1.125
0
0
0
1
0
1.150
1
0
0
1
0
1.175
0
0
0
0
1
1.200
1
0
0
0
1
1.225
0
0
0
0
0
1.250
1
0
0
0
0
1.275
0
1
1
1
1
1.300
1
1
1
1
1
1.325
0
1
1
1
0
1.350
1
1
1
1
0
1.375
0
1
1
0
1
1.400
1
1
1
0
1
1.425
0
1
1
0
0
1.450
1
1
1
0
0
1.475
0
1
0
1
1
1.500
1
1
0
1
1
1.525
0
1
0
1
0
1.550
1
1
0
1
0
1.575
0
1
0
0
1
1.600
1
1
0
0
1
1.625
0
1
0
0
0
1.650
1
1
0
0
0
1.675
0
0
1
1
1
1.700
1
0
1
1
1
1.725
0
0
1
1
0
1.750
1
0
1
1
0
1.775
0
0
1
0
1
1.800
1
0
1
0
1
1.825
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
V
CC
CORE
(VDC)
VID25mV
VID3
VID2
VID1
VID0
ISL6562