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參數(shù)資料
| 型號： | FN4871 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Multiple Linear Power Controller with ACPI Control Interface |
| 中文描述： | 多重線性電源控制器ACPI控制接口 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 149K |
| 代理商： | FN4871 |
7
VSEN1 (Pin 3)
Connect this pin to the 3.3V memory output (V
OUT1
). In
sleep states, this pin is regulated to 3.3V through an internal
pass transistor capable of delivering 300mA (typically). The
active-state voltage at this pin is provided from the ATX 3.3V
through a fully on N-MOS transistor. During all operating
states, the voltage at this pin is monitored for under-voltage
events.
VCLK (Pin 6)
This pin is the output of the internal 2.5V clock chip regulator
(V
OUT4
). This internal regulator operates only in active
states (S0, S1/S2) and is shut off during any sleep state,
regardless of the configuration of the chip. This pin is
monitored for under-voltage events.
Description
Operation
The HIP6502B controls 5 output voltages (Refer to Figures
1, 2, and 3). It is designed for microprocessor computer
applications with 3.3V, 5V, 5VSB, and 12V bias input from an
ATX power supply. The IC is composed of three linear
controllers/regulators supplying the computer system’s
3.3V
SB
and PCI slots’ 3.3V
AUX
power (V
OUT3
), the 2.5V
RDRAM and 3.3V SDRAM memory power (V
OUT2
, V
OUT1
),
an integrated regulator dedicated to 2.5V clock chip
(V
OUT4
), a dual switch controller supplying the 5V
DUAL
voltage (V
OUT5
), as well as all the control and monitoring
functions necessary for complete ACPI implementation.
Initialization
The HIP6502B automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5VSB input supply voltage, initiating 3.3V
SB
soft-start operation after exceeding POR threshold. At 3ms
(typically) after 3.3V
SB
finishes its ramp-up, the EN5VDL
status is latched in and the chip proceeds to ramp up the
remainder of the voltages, as required.
Operational Truth Table
The EN5VDL pin offers the choice of supporting or disabling
5VDUAL output in S3 and S4/S5 sleep states. Table 1
describes the truth combinations pertaining to this output.
The internal circuitry does not allow the transition from an S3
(suspend to RAM) state to an S4/S5 (suspend to disk/soft
off) state or vice versa. The only ‘legal’ transitions are from
an active state (S0, S1) to a sleep state (S3, S5) and vice
versa.
Functional Timing Diagrams
Figures 4 through 6 are timing diagrams, detailing the power
up/down sequences of all three outputs in response to the
status of the enable (EN5VDL) and sleep-state pins (S3,
S5), as well as the status of the ATX supply.
The status of the EN5VDL pin can only be changed while in
active (S0, S1) states, when the bias supply (5VSB pin) is
below POR level, or during chip shutdown (SS pin shorted to
GND or within 3ms of 5VSB POR); a status change of this
pin while in a sleep state is ignored.
TABLE 1. 5V
DUAL
OUTPUT (V
OUT5
) TRUTH TABLE
EN5VDL
S5
S3
5VDL
COMMENTS
0
1
1
5V
S0, S1 States (Active)
0
1
0
0V
S3
0
0
1
Note
Maintains Previous State
0
0
0
0V
S4/S5
1
1
1
5V
S0, S1 States (Active)
1
1
0
5V
S3
1
0
1
Note
Maintains Previous State
1
0
0
5V
S4/S5
NOTE: Combination Not Allowed.
FIGURE 4. 5V
DUAL
TIMING DIAGRAM FOR EN5VDL = 1;
3.3V
DUAL
/3.3V
SB
5VSB
3.3V,
S3
S5
5VDLSB
DLA
3V3DLSB
3V3DL
5VDL
5V, 12V
HIP6502B
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