參數(shù)資料
型號(hào): FMS9875KGC140
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
封裝: MQFP-100
文件頁(yè)數(shù): 27/31頁(yè)
文件大小: 517K
代理商: FMS9875KGC140
FMS9875
PRODUCT SPECIFICATION
REV. 1.2.15 1/14/02
5
Pin Descriptions
Addressable Memory
Register Map
Pin
Name
Pin No.
Pin Function Description
Power and Ground
VDDA
5, 7, 11, 13, 17, 19, 95, 99, 100
ADC Supply Voltages. Provide a quiet noise free voltage.
VDDP
26, 27, 33, 37, 39
PLL Supply Voltage. Most sensitive supply voltage.
Provide a very quiet noise free voltage.
VDDO
50, 60, 62, 72, 85, 91
Digital Output Supply Voltage. Decouple judiciously to
avoid propagation of switching noise.
GND
1, 6, 8, 12, 14, 18, 28, 29, 32, 36, 38, 40,
41, 42, 49, 59, 61, 71, 84, 90, 92, 93, 94
Ground. Returns for all power supplies. Connect ground
pins to a solid ground-plane.
VREFIN
98
Voltage Reference Input. Common reference input to
RGB converters. Connect to VREFOUT, if internal
reference is used.
VREFOUT
97
Voltage Reference Output. Internal band-gap reference
output. Tie to ground through a 0.1F capacitor.
Name
Address
Function
Default (hex)
PLLN11-4
00
PLL divide ratio, MSBs. PLLN + 1 = total number of
pixels per horizontal line.
69 (1693)
PLLCTRL
01
PLL Control Register.
1. Lower four bits of PLL divide ratio.
2. PLL Subdivide phase.
3. PLL Subdivide ratio.
D0 (1693)
GGY7-0
02
Gain, green/luminance channel. Adjustable from 70 to
140%.
80
GBP7-0
03
Gain, blue/PB channel. Adjustable from 70 to 140%.
80
GRP7-0
04
Gain, red/PR channel. Adjustable from 70 to 140%.
80
OSGY5-0
05
Offset, green/luminance channel. OSR5-0 is stored in
the six upper register bits 7-2. Default value is decimal 32.
80
OSBP5-0
06
Offset, blue/PB channel. OSR5-0 is stored in the six
upper register bits 7-2. Default value is decimal 32.
80
OSRP5-0
07
Offset, red/PR channel. OSR5-0 is stored in the six upper
register bits 7-2. Default value is decimal 32.
80
CD7-0
08
Clamp delay. Delay in pixels from trailing edge of
horizontal sync.
80
CW7-0
09
Clamp width. Width of clamp pulse in pixels.
80
CONFIG 1
0A
Configuration Register No. 1
F4
OSGY5–0
X X
OSBP5–0
X X
OSRP5–0
X X
相關(guān)PDF資料
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FMS9875KGC140X 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100
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