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參數(shù)資料
| 型號(hào)： | FMS7950KWCX |
| 英文描述： | Miscellaneous Clock Generator |
| 中文描述： | 雜項(xiàng)時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大小： | 72K |
| 代理商： | FMS7950KWCX |
PRODUCT SPECIFICATION
FMS7950
2
REV. 1.0.0 1/9/01
Pin Assignments
Pin Description
Pin Name
VDDCOR
Pin #
1
Pin Type
PWR
Description
Power supply for core logic and PLL
Power Connection.
circuitry. Connect to 3.3 Volts nominal.
Feedback Select.
When high, the feedback divide is 8, and when
low, it is 16. It allows for a wider range of input frequencies.
Divider Select:
It divides the clock to a desirable value. See
table 2.
Ground Connection.
Ground for core logic and PLL circuitry.
Connect to the common system ground plane.
Crystal Connection.
An input connection for an external crystal
or oscillator. 18 pF internal cap. It can be used as an external
crystal connection or as an external reference frequency input.
Crystal Connection or External Reference Frequency.
pin has dual functions.
Output Enable.
When high, all outputs are in high impedance.
Normal operation when asserted low.
Power Connection.
Power supply for all the output buffers.
Connect to 3.3 Volts nominal.
Clock Outputs.
These outputs are multiple of the input.
FBsel
2
IN
DIV_SEL(A:D)
3, 4, 5, 6
IN
GNDCOR
7
PWR
X1
8
IN
X2
9
OUT
This
OE
10
IN
VDDOUT
11, 15, 19, 23, 27
PWR
Q
Q
GNDOUT
A
D
; Q
(0:4)
B
; Q
C
(0:1);
12, 14, 16, 18, 20,
22, 24, 26, 28
13, 17, 21, 25, 29
OUT
PWR
Ground Connection.
common system ground plane.
Test Clock.
When REF_SEL is high, all outputs are buffer copy
of TCLK. When REF_SEL is low, TCLK is disabled.
PLL Enable.
When low, PLL is bypassed.
Reference Select.
When low, crystal is used for input. When
high, TCLK is used for input.
Ground for all the outputs. Connect to
TCLK
30
IN
PLL_EN
REF_SEL
31
32
IN
IN
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
G
G
T
R
P
Q
Q
V
QC0
QD0
VDDOUT
QD1
GNDOUT
VDDOUT
QC1
GNDOUT
VDDCOR
FBsel
32-PIN
LQFP
DIV_SEL C
DIV_SEL D
X1
GNDCOR
DIV_SEL B
DIV_SEL A
Q
Q
V
X
O
V
G
Q
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