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參數(shù)資料
| 型號(hào)： | FMS7950KWC |
| 英文描述： | Miscellaneous Clock Generator |
| 中文描述： | 雜項(xiàng)時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | FMS7950KWC |
PRODUCT SPECIFICATION
FMS7950
6
REV. 1.0.0 1/9/01
Application
FMS7950 is one of the simplest form of frequency synthesizer. It uses phase locked loop technology with a divide of “N” in its
feedback path. Its purpose is to generate a large number of different output frequencies, all related to a single, highly stable ref-
erence source. To achieve this, a crystal is connected at X1 and X2. No external components are required since the capacitors
and oscillator are integrated.
Figure 1 depicts the block diagram for FMS7950.
Figure 1.
In general, phase locked loops are governed by the equation:
Equation 1 states that any output can be generated if “N” is varied. In FMS7950, the available dividers are eight or sixteen. These
values are selected by connecting FBsel to ground or VDD. To determine the allowable range of input frequencies for each differ-
ent FBsel setting, the following equation must be used:
If divided by eight is selected, the minimum input range will be:
The maximum input range:
If divide by sixteen is selected, a lower range of input frequency is allowed (12.5–22MHZ). This analysis reveals that if lower
input frequency is available, FBsel must be connected to GND. On the other hand, higher input frequencies require FBsel to be
connected to VDD.
In practical applications, it is always the output frequency that is known and one must work backwards to determine the input
and VCO frequencies. The best approach to explain is by an example. Assume an application requires the following output
frequencies:
Phase
Detected
Osc.
X1
X2
Loop
Filter
VCO
P
QA
Q
QB
R
QC(0:1)
S
QD(0:4)
F
OUT
N
F
REF
=
Equation 1
F
REF
F
VCO
N
÷
=
Equation 2
F
REF_MIN
200
25 MHZ
8
÷
=
=
F
REF_MAX
360
43.75 MHZ
8
÷
=
=
QA
QB
QC & QD
133.33 MHZ
66.66 MHZ
33.33 MHZ
=
=
=
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