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參數(shù)資料
| 型號(hào)： | FMS6364AMTC14X |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DVR VID FILTER SD/HD 14TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻濾波器 |
| 應(yīng)用： | 錄音機(jī)，機(jī)頂盒 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | FMS6364AMTC14XDKR |
ICS83026AMI REVISION C AUGUST 26, 2009
7
2009 Integrated Device Technology, Inc.
ICS83026I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Parameter Measurement Information, continued
Propagation Delay
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 =
0.609.
Figure 1. Single-Ended Signal Driving Differential Input
nCLK
Q0, Q1
CLK
t
PD
V
DD
2
V_REF
Single Ended Clock Input
VDD
CLK
nCLK
R1
1K
C1
0.1u
R2
1K
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