2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6346E Rev.3.0.0
11
FMS6346E
—
Six-Channel,
Selectable
SD/HD
Volt
agePlus
Video
Filter
Driver
with
Disable
The same method can be used to bias the clamp
signals.
LCVF
Bias
Input
0.1μF
External video
source must
be AC coupled
500mV +/-350mV
75
7.5M
75
Figure 15. Biased SCART with DC-Coupled Outputs
The same circuits can be used with AC-coupled outputs
if desired, as shown in Figure 16.
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Inactive
0V - 1.4V
220F
75
Figure 16. DC-Coupled Inputs, AC-Coupled Outputs
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Active
0.1μF
0V - 1.4V
75
220μF
Figure 17. Coupled Inputs, AC-Coupled Outputs
LCVF
Clamp
Active
0.1F
External video
source must
be AC coupled.
500mV +/-350mV
220F
75W
7.5MW
75W
Figure 18. Biased SCART with AC-Coupled Outputs
Note:
6.
The video tilt or line time distortion is dominated by
the AC-coupling capacitor. The value may need to
be increased beyond 220μF to obtain satisfactory
operation in some applications.
Power Dissipation
The FMS6346E output drive conguration must be
considered when calculating overall power dissipation.
Care must be taken not to exceed the maximum die
junction temperature. The following example can be
used to calculate the power dissipation and internal
temperature rise:
TJ = TA + Pd θJA
(1)
where Pd = PCH1 + PCH2 + PCHx and
PCHx = VS ICH - (VO
2/R
L)
where VO = 2VIN + 0.280V
ICH = (ICC / 6) + (VO/RL)
VIN = RMS value of input signal
ICC = 50mA, VS = 3.3V
RL = channel load resistance
Board layout affects thermal characteristics. Refer to the
Layout Considerations section for more information.
Output Considerations
The FMS6346E outputs are DC offset from the input by
150mV; therefore VOUT = 2VIN DC+150mV. This offset
is required to obtain optimal performance from the
output driver and is held at the minimum value to
decrease the standing DC current into the load. Since
the FMS6346E has a 2 x (6dB) gain, the output is
typically connected via a 75 series back-matching
resistor followed by the 75 video cable. Due to the
inherent divide by two of this configuration, the blanking
level at the load of the video signal is always less then
1V. When AC-coupling the output, ensure that the
coupling capacitor passes the lowest frequency content
in the video signal and that line time distortion (video tilt)
is kept as low as possible.
The selection of the coupling capacitor is a function of
the subsequent circuit input impedance and the leakage
current of the input driven. To obtain the highest quality
output video signal, the series termination resistor must
be placed as close to the device output pin as possible.
This greatly reduces the parasitic capacitance and
inductance effect on the output driver. The distance from
the device pin to the series termination resistor should
be no greater than 12.7mm (0.5in).
Routing Trace
≤ 12.7mm
75-Ohm Series
Termination Resistor
Lead
Pad
Pad for
Resistor
Lead
Figure 19. Termination Resistor Placement