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參數(shù)資料
| 型號： | FMS3820KRC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, 8 BITS INPUT LOADING, 1700 us SETTLING TIME, 8-BIT DAC, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 62K |
| 代理商： | FMS3820KRC |
FMS3818/3820
PRODUCT SPECIFICATION
10
REV. 1.1.7 9/25/01
Pr
eliminar
y
Infor
mation
Timing Diagram
CLK
PIXEL DATA
& CONTROLS
OUTPUT
DataN
DataN+1
DataN+2
tPWL
tS
tH
50%
5%/FS
90%
10%
tDO
tSET
tF
tR
tPWH
1/fS
Applications Information
Figure 4 illustrates a typical FMS3818/3820 interface
circuit. In this example, an optional 1.2 Volt bandgap
reference is connected to the VREF output, overriding the
internal voltage reference source.
Grounding
It is important that the FMS3818/3820 power supply is
well-regulated and free of high-frequency noise. Careful
power supply decoupling will ensure the highest quality
video signals at the output of the circuit. The FMS3818/3820
has separate analog and digital circuits. To keep digital
system noise away from the D/A converter, it is recom-
mended that power supply voltages come from the system
analog power source and all ground connections (GND) be
made to the analog ground plane. Power supply pins should
be individually decoupled at the pin.
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly inuenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor D/A conversion. Consider the following
suggestions when doing the layout:
1.
Keep the critical analog traces (VREF, IREF, COMP,
IOS, IOR, IOG) as short as possible and as far as
possible from all digital signals. The FMS3818/3820
should be located near the board edge, close to the
analog output connectors.
2.
The power plane for the FMS3818/3820 should be
separate from that which supplies the digital circuitry.
A single power plane should be used for all of the VDD
pins. If the power supply for the FMS3818/3820 is the
same as that of the system's digital circuitry, power to
the FMS3818/3820 should be decoupled with 0.1F and
0.01F capacitors and isolated with a ferrite bead.
3.
The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
4.
If the digital power supply has a dedicated power plane
layer, it should not be placed under the FMS3818/3820,
the voltage reference, or the analog outputs. Capacitive
coupling of digital power supply noise from this layer to
the FMS3818/3820 and its related analog circuitry can
have an adverse effect on performance.
5.
CLK should be handled carefully. Jitter and noise on
this clock will degrade performance. Terminate the
clock line carefully to eliminate overshoot and ringing.
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