參數(shù)資料
型號: FMS3818
廠商: Fairchild Semiconductor Corporation
英文描述: Triple Video D/A Converter 3 x 8 bit, 180 Ms/s
中文描述: 三路視頻D / A轉(zhuǎn)換3 × 8位,180 MS / s的
文件頁數(shù): 9/13頁
文件大?。?/td> 178K
代理商: FMS3818
PRODUCT SPECIFICATION
FMS3818
REV. 1.2.2 11/11/01
9
Timing Diagram
CLK
PIXEL DATA
& CONTROLS
OUTPUT
DataN
DataN+1
DataN+2
t
PWL
t
S
t
H
50%
3%/FS
90%
10%
t
D
t
SET
t
F
t
R
t
PWH
1/f
S
Applications Information
Figure 4 illustrates a typical FMS3818 interface
circuit. In this example, an optional 1.2 Volt bandgap
reference is connected to the V
REF
output, overriding the
internal voltage reference source.
Grounding
It is important that the FMS3818 power supply is
well-regulated and free of high-frequency noise. Careful
power supply decoupling will ensure the highest quality
video signals at the output of the circuit. The FMS3818 has
separate analog and digital circuits. To keep digital
system noise away from the D/A converter, it is recom-
mended that power supply voltages come from the system
analog power source and all ground connections (GND) be
made to the analog ground plane. Power supply pins should
be individually decoupled at the pin.
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor D/A conversion. Consider the following
suggestions when doing the layout:
1.
Keep the critical analog traces (V
REF
, I
REF
, COMP,
IO
S
, IO
R
, IO
G
) as short as possible and as far as
possible from all digital signals. The FMS3818 should
be located near the board edge, close to the
analog output connectors.
2.
The power plane for the FMS3818 should be
separate from that which supplies the digital circuitry.
A single power plane
should be used for all of the V
DD
pins. If the power supply for the FMS3818 is the same
as that of the system's digital circuitry, power to the
FMS3818 should be decoupled with 0.1μF and 0.01μF
capacitors and isolated with a ferrite bead.
3.
The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
4.
If the digital power supply has a dedicated power plane
layer, it should not be placed under the FMS3818, the
voltage reference, or the analog outputs. Capacitive cou-
pling of digital power supply noise from this layer to the
FMS3818 and its related analog circuitry can have an
adverse effect on performance.
5.
CLK should be handled carefully. Jitter and noise on
this clock will degrade performance. Terminate the
clock line carefully to eliminate overshoot and ringing.
Improved Transition Times
Output shunt capacitance dominates slowing of output
transition times, whereas series inductance causes a small
amount of ringing that affects overshoot and settling time.
With a doubly terminated 75
load, transition times can be
improved by matching the capacitive impedance output of
the FMS3818. Output capacitance can be matched with a
220 nH inductor in series with the 75
source termination.
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