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參數(shù)資料
| 型號： | FMS3815KRC_NL |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 168K |
| 代理商： | FMS3815KRC_NL |
FMS3810/3815
PRODUCT SPECIFICATION
4
REV. 1.08 12/21/00
Pin Descriptions
Pin
Name
Pin Number
Value
Pin Function Description
LQFP
Clock and Pixel I/O
CLK
26
TTL
Clock Input. The clock input is TTL-compatible and all pixel data is
registered on the rising edge of CLK. It is recommended that CLK be
driven by a dedicated TTL buffer to avoid reflection induced jitter,
overshoot, and undershoot.
R7-0
G7-0
B7-0
47-40
9-2
23-16
TTL
Red, Green, and Blue Pixel Inputs. TTL-compatible RGB digital inputs
are registered on the rising edge of CLK.
Controls
SYNC
11
TTL
Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE (7.62 mA)
current source which forms a sync pulse on any D/A converter output
connected to IOS. SYNC is registered on the rising edge of CLK along
with pixel data and has the same pipeline latency as BLANK and pixel
data. SYNC does not override any other data and should be used only
during the blanking interval. If the system does not require sync pulses,
SYNC and IOS should be connected to GND.
BLANK
10
TTL
Blanking Input. When BLANK is LOW, pixel inputs are ignored and the
D/A converter outputs are driven to the blanking level. BLANK is
registered on the rising edge of CLK and has the same two-pipe latency
as SYNC and Data.
Video Outputs
IOR
IOG
IOB
33
32
29
0.714 Vp-p
Red, Green, and Blue Current Outputs. Current source outputs can
drive RS-343A/SMPTE-170M compatible levels into doubly-terminated
75 Ohm lines. Sync pulses may be added to the green output.
When SYNC is HIGH, the current added to IOG is:
IOS = 3.64 (VREF / RREF)
Voltage Reference
VREF
35
+1.235 V
Voltage Reference Input/Output. Internal 1.235V voltage reference is
available on this pin. An external +1.235 Volt reference may be applied to
this pin to override the internal reference. Decoupling VREF to GND with
a 0.1F ceramic capacitor is required.
RREF
36
590
Current-setting Resistor. Full-scale output current of each D/A
converter is determined by the value of the resistor connected between
RREF and GND. Nominal value of RREF is found from:
RREF = 9.1 (VREF/IFS)
where IFS is the full-scale (white) output current (amps) from the
D/A converter (without sync). Sync is 0.4 IFS.
D/A full-scale (white) current may also be calculated from:
IFS = VFS/RL
Where VFS is the white voltage level and RL is the total resistive load
(ohms) on each D/A converter. VFS is the blank to full-scale voltage.
COMP
34
0.1 F
Compensation Capacitor. A 0.1 F ceramic capacitor should be
connected between COMP and VDD to stabilize internal bias circuitry.
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| FMS3818KRCX | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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