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參數(shù)資料
| 型號： | FMS3125KRC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | TRIPLE, PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 143K |
| 代理商： | FMS3125KRC |
FMS3110/3115/3120/3125
PRODUCT SPECIFICATION
8
REV. 1.03 9/19/00
Electrical Characteristics
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. Minimum/Maximum values with VDD = Max and TA = Min.
3. VREF = 1.235V, RLOAD = 37.5
, RREF = 540
Switching Characteristics
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. VREF = 1.235V, RLOAD = 37.5
, RREF = 590.
System Performance Characteristics
Notes:
1. Values shown in Typ column are typical for VDD = +5V and TA = 25°C.
2. VREF = 1.235V, RLOAD = 37.5
, RREF = 590.
Parameter
Conditions3
Min
Typ1
Max
Units
IDD
Power Supply Current2
VDD = Max
125
mA
PD
Total Power Dissipation2
VDD = Max
655
mW
RO
Output Resistance
100
k
CO
Output Capacitance
IOUT = 0mA
30
pF
IIH
Input Current, HIGH
VDD = Max, VIN = 2.4V
-5
A
IIL
Input Current, LOW
VDD = Max, VIN = 0.4V
5
A
IREF
VREF Input Bias Current
0
±100
A
VREF
Reference Voltage Output
1.235
V
VOC
Output Compliance
Referred to VDD
-0.4
0
+1.5
V
CDI
Digital Input Capacitance
4
10
pF
Parameter
Conditions2
Min
Typ1
Max
Units
tD
Clock to Output Delay
VDD = Min
10
15
ns
tSKEW
Output Skew
1
2
ns
tR
Output Risetime
10% to 90% of Full Scale
3
ns
tF
Output Falltime
90% to 10% of Full Scale
3
ns
Parameter
Conditions2
Min
Typ
1
Max
Units
ELI
Integral Linearity Error
VDD, VREF = Nom
±0.1
±0.25
%/FS
ELD
Differential Linearity Error
VDD, VREF = Nom
±0.1
±0.25
%/FS
EDM
DAC to DAC Matching
VDD, VREF = Nom
3
10
%
PSR
Power Supply Rejection Ratio
0.05
%/%
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