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參數(shù)資料
| 型號(hào)： | FMS3120KRC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | TRIPLE, PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 143K |
| 代理商： | FMS3120KRC |
FMS3110/3115/3120/3125
PRODUCT SPECIFICATION
2
REV. 1.03 9/19/00
Functional Description
Within the FMS3110/3115/3120/3125 are three identical 10-
bit D/A converters, each with a current source output. Exter-
nal loads are required to convert the current to voltage out-
puts. Data inputs RGB7-0 are overridden by the BLANK
input. SYNC = H activates, sync current from IOS for sync-
on-green video signals.
Digital Inputs
All digital inputs are TTL-compatible. Data is registered on
the rising edge of the CLK signal. Following one stage of
pipeline delay, the analog output changes tDO after the rising
edge of CLK.
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 1
and Table 1) of the D/A converters during CRT retrace inter-
vals. BLANK forces the D/A outputs to the blanking level
while SYNC = L turns off a current source that is connected
to the green D/A converter. SYNC = H adds a 40 IRE sync
pulse to the green output, SYNC = L sets the green output to
0.0 Volts during the sync tip. SYNC and BLANK are regis-
tered on the rising edge of CLK.
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = Low, data
inputs and the pedestal are disabled.
Figure 1. Nominal Output Levels
D/A Outputs
Each D/A output is a current source. To obtain a voltage out-
put, a resistor must be connected to ground. Output voltage
depends upon this external resistor, the reference voltage,
and the value of the gain-setting resistor connected between
RREF and GND.
Normally, a source termination resistor of 75 Ohms is con-
nected between the D/A current output pin and GND near
the D/A converter. A 75 Ohm line may then be connected
with another 75 Ohm termination resistor at the far end of
the cable. This “double termination” presents the D/A con-
verter with a net resistive load of 37.5 Ohms.
The FMS3110/3115/3120/3125 may also be operated with a
single 75 Ohm terminating resistor. To lower the output volt-
age swing to the desired range, the nominal value of the
resistor on RREF should be doubled.
Voltage Reference
All three D/A converters are supplied with a common volt-
age reference. Internal bandgap voltage reference voltage is
+1.235 Volts with a 3K
source resistance. An external volt-
age reference may be connected to the VREF pin, overriding
the internal voltage reference.
A 0.1F capacitor must be connected between the COMP
pin and VDD to stabilize internal bias circuitry and ensure
low-noise operation.
Power and Ground
Required power is a single +5.0 Volt supply. To minimize
power supply induced noise, analog +5V should be connected
to VDD pins with 0.1 and 0.01 F decoupling capacitors
placed adjacent to each VDD pin or pin pair.
The high slew-rate of digital data makes capacitive coupling
to the outputs of any D/A converter a potential problem.
Since the digital signals contain high-frequency components
of the CLK signal, as well as the video output signal, the
resulting data feedthrough often looks like harmonic distor-
tion or reduced signal-to-noise performance. All ground pins
should be connected to a common solid ground plane for
best performance.
data: 660 mV max.
pedestal: 54 mV
sync: 286 mV
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