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參數(shù)資料
| 型號： | FM3808 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 4Kb FRAM Serial 3V Memory |
| 中文描述： | 4Kb的鐵電串行3V的記憶 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 191K |
| 代理商： | FM3808 |
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FM3808
Rev 1.1
May 2003
Page 16 of 28
must remain high for at least the minimum precharge
timing specification. The user dictates the beginning
of this operation since a precharge will not begin until
/CE rises. However, the device has a maximum /CE
low time specification that must be satisfied.
Memory Architecture
FRAM memory internally operates with a read and
restore mechanism. Therefore, each read and write
cycle involves a change of state. The memory
architecture is based on an array of rows and
columns. Each access causes an endurance cycle for
an entire 32-bit row (4 bytes). The memory array is
divided into 32 blocks, each 1Kx8. The 5-upper
address lines decode the block selection as shown in
Figure 6. Data targeted for significantly different
numbers of cycles should be located in separate
blocks since memory rows do not extend across block
boundaries.
Each block of 1Kx8 consists of 256 rows and 4
column address locations. The address lines A0-A7
decode row selection and A8-A9 lines decode column
selection. This scheme facilitates a relatively uniform
distribution of cycles across the rows of a block. By
allowing the address LSBs to decode row selection,
the user avoids applying multiple cycles to the same
row when accessing sequential data. For example,
256 bytes can be accessed sequentially without
accessing the same row twice. In this example, one
cycle would be applied to each row. An entire block
of 1Kx8 can be read or written with only four cycles
applied to each row. Figure 7 illustrates the
organization within a memory block.
Figure 6. Address Blocks
Figure 7. Row and Column Organization
Block 3
Block 31
Block 30
Block 29
Block 28
Block 2
Block 1
Block 0
FFFFh
FC00h
FBFFh
F800h
F7FFh
F400h
F3FFh
F000h
0FFFh
0C00h
0BFFh
0800h
07FFh
0400h
03FFh
0000h
Block 4
A14-A10
00100b
R
R
R
R
R
R
R
A0-A7
00h
FFh
00b
01b
10b
11b
A9-A8
01h 02h 03h
R
FEh
FDh
FCh
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FM3808-70-T | 4Kb FRAM Serial 3V Memory |
| FM3808DK | 4Kb FRAM Serial 3V Memory |
| FMA10A | General Purpose(Dual Digital Transistor)(通用(雙數(shù)字晶體管)) |
| FMA11A | Emitter Common (Dual Digital Transistors)(公共發(fā)射級(雙數(shù)字晶體管)) |
| FMA1 | General purpose (dual digital transistors) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FM3808_06 | 制造商:RAMTRON 制造商全稱:RAMTRON 功能描述:256Kb Bytewide FRAM w/ Real-Time Clock |
| FM3808-70-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Kb Bytewide FRAM w/ Real-Time Clock |
| FM3808DK | 制造商:RAMTRON 制造商全稱:RAMTRON 功能描述:256Kb Bytewide FRAM w/ Real-Time Clock |
| FM3808-S | 制造商:Ramtron International Corporation 功能描述:FRAM RTC 256K SMD 3808 TSOP32 |
| FM3808-SG | 制造商:Ramtron International Corporation 功能描述:FRAM RTC 256K SMD 3808 TSOP32 |
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