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參數(shù)資料
| 型號： | FM3580MT20 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2mm TERMINAL STRIP |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 107K |
| 代理商： | FM3580MT20 |
8
F
www.fairchildsemi.com
FM3580 Rev. A.5
Y[0:4]
Non_Mux_Out
I[0:4]
I[0:4]
Mux_Sel
/Override
Level
/Override
Level
Mux_Sel
MXSB MXSA
I4
I3
I2
I1
I0
BIT 7
BIT 0
MXSB MXSA
I4
NMO
I3
I2
I1
I0
BIT 7
BIT 0
SOPR-A
μ
SOPR-B
5
5
2
NMO
Output
Control
Output
Control
&
Latch
Note:
Bit7 and Bit 6 are common to both the SOPR-A and SOPR-B registers
Multiplexer Block Diagram
Table 1. Multiplexer Path Control
/Override
Signal
Mux_Sel
Signal
MXSB
Bit
MXSA
Bit
Y-Port Outputs
Y[4:0]
Non_Mux_Out
Signal
0
0
X
X
Logic
“
0
”
Logic
“
0
”
X
1
X
X
I-Port Inputs
I[4:0]
Latched Non_Mux_Out
(see Note)
1
0
0
0
Data from SOPR-A register
Data from SOPR-A register
0
1
Data from SOPR-B register
Data from SOPR-B register
1
0
I-Port Inputs
I[4:0]
Latched Non_Mux_Out
(see Note)
1
1
Reserved (Do Not Use)
Reserved (Do Not Use)
Note:
Latched Non_Mux_Out is the data that was present at NMO multiplexer input during the rising edge of Mux_sel signal.
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