參數(shù)資料
型號: FM27C040QE150
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4,194,304-Bit 512K x 8 High Performance CMOS EPROM
中文描述: 512K X 8 UVPROM, 150 ns, CDIP32
封裝: WINDOWED, CERDIP-32
文件頁數(shù): 4/11頁
文件大小: 106K
代理商: FM27C040QE150
4
www.fairchildsemi.com
FM27C040 Rev. A
F
AC Test Conditions
Output Load
1 TTL Gate and C
L
= 100 pF (Note 8)
Input Rise and Fall Times
5 ns
Input Pulse Levels
0.45V to 2.4V
Timing Measurement Reference Level (Note 10)
Inputs
Outputs`
0.8V and 2V
0.8V and 2V
AC Waveforms
(Notes 6, 7, 9)
Note 1:
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 3:
OE may be delayed up to t
ACC
- t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4:
The t
and t
compare level is determined as follows:
High to TRI-STATE
, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5:
TRI-STATE may be attained using OE or CE .
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
μ
F ceramic capacitor be used on every device
between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8:
1 TTL Gate: I
= 1.6 mA, I
= -400
μ
A.
C
L
: 100 pF includes fixture capacitance.
Note 9:
V
PP
may be connected to V
CC
except during programming.
Note 10:
Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Addresses Valid
Valid Output
Hi-Z
2V
0.8V
2V
0.8V
2V
0.8V
ADDRESSES
OUTPUT
CE
OE
tCE
2V
0.8V
(Note 3)
(Note 3)
tDF
(Note 4, 5)
(Note 4, 5)
tOH
Hi-Z
tOE
ACC
t
CF
t
DS800033-4
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