參數(shù)資料
型號(hào)： FM25W256-G
廠商： Electronic Theatre Controls, Inc.
英文描述： 256Kb FRAM Wide Voltage Serial Memory
中文描述： 寬電壓的256Kb串行FRAM的記憶
文件頁(yè)數(shù)： 5/13頁(yè)
文件大?。?/td> 165K
代理商： FM25W256-G
FM25W256
Rev. 1.0
Aug. 2004
Page 5 of 13
Power Up to First Access
The FM25W256 is not accessible for a period of time
(10 ms) after power up. Users must comply with the
timing parameter t
PU
, which is the minimum time
from V
DD
(min) to the first /CS low.
Data Transfer
All data transfers to and from the FM25W256 occur
in 8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25W256. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the status
register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-code Commands
Name
Description
WREN
Set Write Enable Latch
WRDI
Write Disable
RDSR
Read Status Register
WRSR
Write Status Register
READ
Read Memory Data
WRITE
Write Memory Data
Op-code
0000
0110b
0000
0100b
0000
0101b
0000
0001b
0000
0011b
0000
0010b
WREN - Set Write Enable Latch
The FM25W256 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no effect on the state of this bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further
writes without another WREN command. Figure 5
illustrates the WREN command bus configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
Hi-Z
0 1 2 3 4 5 6 7
0 0 0 0
0 1 1 0
CS
SCK
SI
SO
Figure 5. WREN Bus Configuration
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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FM25W256-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Kb FRAM Wide Voltage Serial Memory
FM25W3S-K121 制造商:FCT Group 功能描述:
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