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參數(shù)資料
| 型號： | FM25CL04-S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 4Kb FRAM Serial 3V Memory |
| 中文描述： | 4Kb的鐵電串行3V的記憶 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 98K |
| 代理商： | FM25CL04-S |
FM25CL04
Rev. 1.0
July 2003
Page 6 of 11
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR op-
code, the FM25CL04 will return one byte with the
contents of the Status register. The Status register is
described in detail in a later section.
WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive.
Prior to sending the WRSR command, the user must
send a WREN command to enable writes. Note that
executing a WRSR command is a write operation
and therefore clears the Write Enable Latch. The bus
configuration of RDSR and WRSR are shown
below.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration
Status Register & Write Protection
The write protection features of the FM25CL04 are
multi-tiered. Taking the /WP pin to a logic low state
is the hardware write protect function. All write
operations are blocked when /WP is low. To write the
memory with /WP high, a WREN op-code must first
be issued. Assuming that writes are enabled using
WREN and by /WP, writes to memory are controlled
by the Status register. As described above, writes to
the status register are performed using the WRSR
command and subject to the /WP pin. The Status
register is organized as follows.
Table 2. Status Register
Bit
7
6
5
4
Name
0
0
0
0
Bits 0 and 7-4 are fixed at 0 and cannot be modified.
Note that the Ready bit in many EEPROMs is
unnecessary as the FRAM writes in real-time and is
never busy. The BP1 and BP0 control software write
protection features. They are nonvolatile! The WEL
3
BP1
2
BP0
1
WEL
0
0
flag indicates the state of the Write Enable Latch.
Writing the WEL bit in the status register has no
effect.
BP1 and BP0 are memory block write protection
bits. They specify portions of memory that are write
protected as shown in the following table.
Table 3. Block Memory Write Protection
BP1
BP0
Protected Address Range
0
0
None
0
1
180h to 1FFh (upper )
1
0
100h to 1FFh (upper )
1
1
000h to 1FFh (all)
The BP1 and BP0 bits allow software to selectively
write protect the array. These settings are only used
when the /WP pin is inactive and the WREN
command has been issued. The following table
summarizes the write protection conditions.
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相關(guān)代理商/技術(shù)參數(shù) |
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| FM25CL64 | 制造商:RAMTRON 制造商全稱:RAMTRON 功能描述:64Kb FRAM Serial 3V Memory |
| FM25CL64_07 | 制造商:RAMTRON 制造商全稱:RAMTRON 功能描述:64Kb FRAM Serial 3V Memory |
| FM25CL64B | 制造商:RAMTRON 制造商全稱:RAMTRON 功能描述:64Kb Serial 3V F-RAM Memory |
| FM25CL64B_13 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64Kb Serial 3V F-RAM Memory |
| FM25CL64B-DG | 功能描述:F-RAM 64Kb Serial SPI 3V FRAM RoHS:否 存儲容量:512 Kbit 組織:64 K x 8 接口:SPI 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 制造商:Cypress Semiconductor |
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