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參數(shù)資料
| 型號： | FM25C041UVMT8 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | SERIAL EEPROM|512X8|CMOS|TSSOP|8PIN|PLASTIC |
| 中文描述： | 512 X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | TSSOP-8 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 103K |
| 代理商： | FM25C041UVMT8 |
1
www.fairchildsemi.com
FM25C041U Rev. B
F
FM25C041U
4K-Bit SPI Interface
Serial CMOS EEPROM
Block Diagram
February 2002
2002 Fairchild Semiconductor Corporation
Instruction
Decoder
Control Logic
and Clock
Generators
High Voltage
Generator
and
Program
Timer
Instruction
Register
Program
Enable
Data In/Out Register
8 Bits
Data Out
Buffer
Non-Volatile
Status Register
Decoder
Address
Counter/
Register
EEPROM Array
Read/Write Amps
/CS
/HOLD
SCK
V
CC
V
SS
V
PP
/WP
SI
SO
General Description
The FM25C041U is a 4K (4,096) bit serial interface CMOS
EEPROM (Electrically Erasable Programmable Read-Only
Memory). This device fully conforms to the SPI 4-wire protocol
which uses Chip Select (/CS), Clock (SCK), Data-in (SI) and Data-
out (SO) pins to synchronously control data transfer between the
SPI microcontroller and the EEPROM. In addition, the serial
interface allows a minimal pin count, packaging designed to
simplify PC board layout requirements and offers the designer a
variety of low voltage and low power options.
This SPI EEPROM family is designed to work with the 68HC11 or
any other SPI-compatible, high-speed microcontroller and offers
both hardware (/WP pin) and software ("block write") data protec-
tion. For example, entering a 2-bit code into the STATUS REGIS-
TER prevents programming in a selected block of memory and all
programming can be inhibited by connecting the /WP pin to V
SS
;
allowing the user to protect the entire array or a selected section.
In addition, SPI devices feature a /HOLD pin, which allows a
temporary interruption of the datastream into the EEPROM.
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con-
sumption for a continuously reliable non-volatile solution for all
markets.
Functions
I
SPI MODE 1 interface
I
4,096 bits organized as 512 x 8
I
Extended 2.7V to 5.5V operating voltage
I
2.1 MHz operation @ 4.5V - 5.5V
I
Self-timed programming cycle
I
"Programming complete" indicated by STATUS REGISTER
polling
I
/WP pin and BLOCK WRITE protection
Features
I
Sequential read of entire array
I
4 byte "Page write" mode to minimize total write time per
byte
I
/WP pin and BLOCK WRITE protection to prevent inadvert-
ent programming as well as programming ENABLE and
DISABLE opcodes.
I
/HOLD pin to suspend data transfer
I
Typical 1
μ
A standby current (I
SB
) for "L" devices and 0.1
μ
A
standby current for "LZ" devices.
I
Endurance: Up to 1,000,000 data changes
I
Data retention greater than 40 years
SPI is a trademark of Motorola Corporation
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相關(guān)代理商/技術(shù)參數(shù) |
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