參數(shù)資料
型號(hào): FM24CL64
廠商: Electronic Theatre Controls, Inc.
元件分類: DRAM
英文描述: 4Kb FRAM Serial 3V Memory
中文描述: 4Kb的鐵電串行3V的記憶
文件頁(yè)數(shù): 2/11頁(yè)
文件大?。?/td> 77K
代理商: FM24CL64
Ramtron
Figure 1. FM24CL64 Block Diagram
FM24CL64
9 May 2001
2/2
Address
Latch
`
2,048 x 32
FRAM Array
Data Latch
8
SDA
Counter
Serial to Parallel
Converter
Control Logic
SCL
WP
A0-A2
Pin Description
Pin Name
A0-A2
Pin Number
1-3
I/O
I
Pin Description
Address 0-2. These pins are used to select one of up to 8 devices of the
same type on the same two-wire bus. To select the device, the address
value on the three pins must match the corresponding bits contained in
the device address. The address pins are pulled down internally.
Ground
Serial Data Address. This is a bi-directional line for the two-wire
interface. It is open-drain and is intended to be wire-ORed with other
devices on the two-wire bus. The input buffer incorporates a schmitt
trigger for noise immunity and the output driver includes slope control
for falling edges. A pull-up resistor is required.
Serial Clock. The serial clock line for the two-wire interface. Data is
clocked out of the part on the falling edge, and in on the rising edge. The
SCL input also incorporates a schmit trigger input for noise immunity.
Write Protect. When tied to VDD, addresses in the entire memory map
will be write-protected. When WP is connected to ground, all addresses
may be written. This pin is pulled down internally.
Supply Voltage 2.7V to 3.6V.
VSS
SDA
4
5
I
I/O
SCL
6
I
WP
7
I
VDD
8
I
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