is too long. To avoid extra low operating
frequency   and   achieve   brownout   protection,   the
, connected between MOT and GND. A 24k& resistor
?/DIV>
W
=
(2)
The range of the maximum on-time is 10 ~ 50祍.
Peak Current Limiting
The switch current is sensed by one resistor. The signal
is fed into the CS pin and an input terminal of a
comparator. A high voltage on the CS pin terminates
the switching cycle immediately and cycle-by-cycle
current limit is achieved. The designed threshold of the
protection point is 0.82V.
Leading-Edge Blanking (LEB)
A turn-on spike on the CS pin appears when the power
MOSFET is switched on. At the beginning of each
switching pulse, the current-limit comparator is disabled
for around 400ns to avoid premature termination. The
gate drive output cannot be switched off during the
blanking   period.   Conventional   RC   filtering   is   not
necessary, so the propagation delay of current limit
protection can be minimized.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off threshold voltages are fixed
internally at 12V and 9.5V, respectively. This hysteresis
behavior guarantees a one-shot startup with proper
startup resistor and hold-up capacitor. With an ultra-low
startup current of 20礎(chǔ), one 1M& R
IN
is sufficient for
startup under low input line voltage, 85V
rms
. Power
dissipation on R
IN
would be less than 0.1W even under
high line (V
AC
=265V
rms
) condition.
Output Driver
With   low   on   resistance   and   high   current   driving
capability, the output driver can drive an external
capacitive load larger than 3000pF. Cross conduction
current has been avoided to minimize heat dissipation,
improving efficiency and reliability. This output driver is
internally clamped by a 16.5V Zener diode.
Zero-Current Detection (ZCD)
The zero-current detection of the inductor is achieved
using its auxiliary winding. When the stored energy of
the inductor is fully released to output, the voltage on
ZCD goes down and a new switching cycle is enabled
after a ZCD trigger. The power MOSFET is always
turned on with zero inductor current such that turn-on
loss and noise can be minimized. The converter works
in Boundary Mode and peak inductor current is always
exactly twice of the average current. A natural power
factor correction function is achieved with the low-
bandwidth, on-time modulation. An inherent maximum
off time is built in to ensure proper startup operation.
This ZCD pin can be used as a synchronous input.
Noise Immunity
Noise on the current sense or control signal can cause
significant pulse-width jitter, particularly in Boundary
Mode. Slope compensation and a built-in debounce
circuit can alleviate this problem. Because the FL6961
has a single ground pin, high sink current at the output
cannot be returned separately. Good high-frequency or
RF layout practices should be followed. Avoiding long
PCB     traces     and     component     leads,     locating
compensation   and   filter   components   near   to   the
FL6961,   and   increasing   the   power   MOSFET   gate
resistance all improve performance.