參數(shù)資料
型號(hào)： FIN3385MTD
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： CONNECTOR,HEADER,THRU,2 X 10,VERT,,
中文描述： QUAD LINE DRIVER, PDSO56
封裝： 6.10 MM, MO-153, TSSOP-56
文件頁(yè)數(shù)： 4/9頁(yè)
文件大小： 281K
代理商： FIN3385MTD
www.fairchildsemi.com
4
F
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Note 9:
Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after V
CC
reaches 3V and
Power-Down pin is above 1.5V.
Note 10:
This output data pulse position works for TTL inputs except the LVDS output bit mapping difference (see Figure 8). Figure 9 shows the skew
between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
Note 11:
This jitter specification is based on the assumption that PLL has a ref clock with cycle-to-cycle input jitter less than 2ns.
Symbol
t
TCP
t
TCH
t
TCL
t
CLKT
t
JIT
t
XIT
LVDS Transmitter Timing Characteristics
t
TLH
Differential Output Rise Time (20% to 80%)
t
THL
Differential Output Fall Time (80% to 20%)
t
STC
TxIn Setup to TxCLNIn
t
HTC
TxIn Holds to TCLKIn
t
TPDD
Transmitter Power-Down Delay
t
TCCD
Transmitter Clock Input to Clock Output Delay
Transmitter Clock Input to Clock Output Delay
Transmitter Output Data Jitter (f
=
40 MHz) (Note 10)
t
TPPB0
Transmitter Output Pulse Position of Bit 0
t
TPPB1
Transmitter Output Pulse Position of Bit 1
t
TPPB2
Transmitter Output Pulse Position of Bit 2
t
TPPB3
Transmitter Output Pulse Position of Bit 3
t
TPPB4
Transmitter Output Pulse Position of Bit 4
t
TPPB5
Transmitter Output Pulse Position of Bit 5
t
TPPB6
Transmitter Output Pulse Position of Bit 6
Transmitter Output Data Jitter (f
=
65 MHz) (Note 10)
t
TPPB0
Transmitter Output Pulse Position of Bit 0
t
TPPB1
Transmitter Output Pulse Position of Bit 1
t
TPPB2
Transmitter Output Pulse Position of Bit 2
t
TPPB3
Transmitter Output Pulse Position of Bit 3
t
TPPB4
Transmitter Output Pulse Position of Bit 4
t
TPPB5
Transmitter Output Pulse Position of Bit 5
t
TPPB6
Transmitter Output Pulse Position of Bit 6
Transmitter Output Data Jitter (f
=
85 MHz) (Note 10)
t
TPPB0
Transmitter Output Pulse Position of Bit 0
t
TPPB1
Transmitter Output Pulse Position of Bit 1
t
TPPB2
Transmitter Output Pulse Position of Bit 2
t
TPPB3
Transmitter Output Pulse Position of Bit 3
t
TPPB4
Transmitter Output Pulse Position of Bit 4
t
TPPB5
Transmitter Output Pulse Position of Bit 5
t
TPPB6
Transmitter Output Pulse Position of Bit 6
t
JCC
FIN3385 Transmitter Clock Out Jitter
(Cycle-to-Cycle)
See Figure 10
Parameter
Test Conditions
Min
11.76
0.35
Typ
T
0.5
Max
50.0
0.65
Units
ns
T
Transmit Clock Period
Transmit Clock (TxCLKIn) HIGH Time
See Figure 4
Transmit Clock Low Time
TxCLKIn Transition Time (Rising and Failing)
TxCLKIn Cycle-to-Cycle Jitter
0.35
1.0
0.5
0.65
6.0
3.0
T
ns
ns
(10% to 90%) See Figure 5
TxIn Transition Time
1.5
6.0
ns
See Figure 3
0.75
1.5
ns
0.75
1.5
ns
ns
ns
See Figure 4 (f
=
85 MHz)
2.5
0
See Figure 7, (Note 9)
(T
A
=
25
°
C and with V
CC
=
3.3V)
See Figure 6
100
5.5
6.8
ns
ns
2.8
See Figure 9
0.25
a
0.25
2a
0.25
3a
0.25
4a
0.25
5a
0.25
6a
0.25
0
a
0.25
a
+
0.25
2a
+
0.25
3a
+
0.25
4a
+
0.25
5a
+
0.25
6a
+
0.25
ns
ns
a
=
1
2a
3a
4a
ns
ns
ns
f x 7
5a
6a
ns
ns
See Figure 9
0.2
a
0.2
2a
0.2
3a
0.2
4a
0.2
5a
0.2
6a
0.2
0
a
0.2
a
+
0.2
2a
+
0.2
3a
+
0.2
4a
+
0.2
5a
+
0.2
6a
+
0.2
ns
ns
ns
a
=
1
2a
f x 7
3a
4a
5a
ns
ns
ns
6a
ns
See Figure 9
0.2
a
0.2
2a
0.2
3a
0.2
4a
0.2
5a
0.2
6a
0.2
0
0.2
a
+
0.2
2a
+
0.2
3a
+
0.2
4a
+
0.2
5a
+
0.2
6a
+
0.2
370
230
150
ns
a
ns
ns
ns
a
=
1
2a
3a
f x 7
4a
5a
6a
ns
ns
ns
f
=
40 MHz
f
=
65 MHz
f
=
85 MHz
See Figure 12, (Note 10)
350
210
110
ps
t
TPLLS
Transmitter Phase Lock Loop Set Time (Note 11)
10.0
ms
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