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參數(shù)資料
| 型號： | FIN224ACGFX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SERIALIZER/DESERIALIZER 42BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SerDes™ |
| 功能： | 串行器/解串器 |
| 數(shù)據(jù)速率： | 676Mbps |
| 輸入類型： | LVCMOS |
| 輸出類型： | LVCMOS |
| 輸入數(shù)： | 22 |
| 輸出數(shù)： | 22 |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -30°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 42-VFBGA |
| 供應(yīng)商設(shè)備封裝： | 42-BGA |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1217 (CN2011-ZH PDF) |
| 其它名稱： | FIN224ACGFXDKR |
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN224AC Rev.1.1.6
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Terminal Description
Note:
1. The DSO/DSI serial port pins have been arranged such that if one device is rotated 180 degrees with respect to the
other device, the serial connections properly align without the need for any traces or cable signals to cross. Other
layout orientation may require that traces or cables cross.
Terminal
Name
I/O Type
Number of
Terminals
Description of Signals
DP[1:20]
I/O
20
LVCMOS parallel I/O, Direction controlled by DIRI pin
DP[21:22]
I
2
LVCMOS parallel unidirectional inputs
DP[23:24]
O
2
LVCMOS unidirectional parallel outputs
CKREF
IN
1
LVCMOS clock input and PLL reference
STROBE
IN
1
LVCMOS strobe signal for latching data into the serializer
CKP
OUT
1
LVCMOS word clock output
DSO+ / DSI-
DSO- / DSI+
DIFF-I/O
2
CTL differential serial I/O data signals(1.)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO(I)+: Positive signal of DSO(I) pair
DSO(I)-: Negative signal of DSO(I) pair
CKSI+
CKSI-
DIFF-IN
2
CTL differential deserializer input bit clock
CKSI: Refers to signal pair
CKSI+: Positive signal of CKSI pair
CKSI-: Negative signal of CKSI pair
CKSO+
CKSO-
DIFF-OUT
2
CTL differential serializer output bit clock
CKSO: Refers to signal pair
CKSO+: Positive signal of CKSO pair
CKSO-: Negative signal of CKSO pair
S1
IN
1
LVCMOS mode selection terminals used to select frequency range for
the reflect, CKREF
S2
IN
1
DIRI
IN
1
LVCMOS control input used to control direction of data flow:
DIRI = “1” Serializer
DIRI = “0” Deserializer
DIRO
OUT
1
LVCMOS control output inversion of DIRI
VDDP
Supply
1
Power supply for parallel I/O and translation circuitry
VDDS
Supply
1
Power supply for core and serial I/O
VDDA
Supply
1
Power supply for analog PLL circuitry
GND
Supply
2
For ground signals (2 for BGA, 1 for MLP)
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