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    參數(shù)資料
    型號: FIN210ACMLX
    廠商: Fairchild Semiconductor
    文件頁數(shù): 5/17頁
    文件大?。?/td> 0K
    描述: IC SER/DES 10BIT 32-MLP
    標(biāo)準(zhǔn)包裝: 3,000
    功能: 串行器/解串器
    輸入類型: LVCMOS
    輸出類型: 串行
    輸入數(shù): 10
    輸出數(shù): 1
    電源電壓: 1.65 V ~ 3.6 V
    工作溫度: -30°C ~ 70°C
    安裝類型: 表面貼裝
    封裝/外殼: 32-WFQFN 裸露焊盤
    供應(yīng)商設(shè)備封裝: 32-MLP(5x5)
    包裝: 帶卷 (TR)
    SC16IS741_1
    NXP B.V. 2010. All rights reserved.
    Product data sheet
    Rev. 01 — 29 April 2010
    13 of 52
    NXP Semiconductors
    SC16IS741
    Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
    7.6 Sleep mode
    Sleep mode is an enhanced feature of the SC16IS741 UART. It is enabled when EFR[4],
    the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when:
    The serial data input line, RX, is idle (see Section 7.7 “Break and time-out
    The TX FIFO and TX shift register are empty.
    There are no interrupts pending except THR.
    Remark: Sleep mode will not be entered if there is data in the RX FIFO.
    In Sleep mode, the clock to the UART is stopped. Since most registers are clocked using
    these clocks, the power consumption is greatly reduced. The UART will wake up when
    any change is detected on the RX line, when there is any change in the state of the
    modem input pins, or if data is written to the TX FIFO.
    Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be
    done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
    before writing to DLL or DLH.
    7.7 Break and time-out conditions
    When the UART receives a number of characters and these data are not enough to set off
    the receive interrupt (because they do not reach the receive trigger level), the UART will
    generate a time-out interrupt instead, 4 character times after the last character is
    received. The time-out counter will be reset at the center of each stop bit received or each
    time the receive FIFO is read.
    A break condition is detected when the RX pin is pulled LOW for a duration longer than
    the time it takes to send a complete character plus Start, Stop and Parity bits. A break
    condition can be sent by setting LCR[6]. When this happens the TX pin will be pulled LOW
    until LSR[6] is cleared by the software.
    7.8 Programmable baud rate generator
    The SC16IS741 UART contains a programmable baud rate generator that takes any clock
    input and divides it by a divisor in the range between 1 and (216 – 1). An additional
    divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in
    Figure 10. The output frequency of the baud rate generator is 16 times the baud rate. The
    formula for the divisor is given in Equation 1:
    (1)
    where:
    prescaler = 1, when MCR[7] is set to ‘0’ after reset (divide-by-1 clock selected)
    prescaler = 4, when MCR[7] is set to ‘1’ after reset (divide-by-4 clock selected).
    Remark: The default value of prescaler after reset is divide-by-1.
    Figure 10 shows the internal prescaler and baud rate generator circuitry.
    divisor
    XTAL1 crystal input frequency
    prescaler
    -----------------------------------------------------------------------------------
    desired baud rate
    16
    ×
    -----------------------------------------------------------------------------------------
    =
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