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參數(shù)資料
| 型號： | FIN1217MTDX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SERIALIZER/DESERIAL 48-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 串行器/解串器 |
| 數(shù)據(jù)速率： | 1.785Gbps |
| 輸入類型： | LVTTL |
| 輸出類型： | LVDS |
| 輸入數(shù)： | 21 |
| 輸出數(shù)： | 3 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | FIN1217MTDXDKR |
2003 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN1215 / FIN1216 / FIN1217 Rev. 1.0.3
18
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LVD
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Serializers
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-S
erializers
AC Loadings and Waveforms (Continued)
Note: tRSKM is the budget for the cable skew and source clock skew plus Inter-Symbol Interference (ISI).
The minimum and maximum pulse position values are based on the bit position of each of the seven bits within
the LVDS data stream across PVT (Process, Voltage Supply, and Temperature).
Figure 22.
Receiver LVDS Input Skew Margin
Note: This jitter pattern is used to test the jitter response (clock out) of the device over the power supply range with
worst jitter ±ns (cycle-to-cycle) clock input. The specific test methodology is as follows:
Switching input data TxIn0 to TxIn20 at 0.5MHz and the input clock is shifted to left -3ns and to
the right +3ns when data is HIGH (by switching between CLK1 and CLK2 in Figure 11).
The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources.
Jumping between two clock sources to simulate the worst-case of clock edge jump (3ns) from
graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range
with 100mV noise (VCC noise frequency <2MHz).
Figure 23.
Jitter Pattern
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FIN1217MTDX_Q | 功能描述:LVDS 接口集成電路 Serial/De-Serializer LVDS 21Bit RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| FIN1218 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:LVDS 21-Bit Serializers/De-Serializers |
| FIN1218MTD | 功能描述:LVDS 接口集成電路 LVDS 21-Bit RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| FIN1218MTD_Q | 功能描述:功率驅(qū)動器IC LVDS 21-Bit RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時間: 下降時間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| FIN1218MTDX | 功能描述:LVDS 接口集成電路 LVDS 21-Bit RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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