參數(shù)資料
型號: FIN1108MTDX
英文描述: REPEATER INTERFACE|TSSOP|48PIN|PLASTIC
中文描述: 中繼器接口|采用TSSOP | 48PIN |塑料
文件頁數(shù): 4/7頁
文件大?。?/td> 408K
代理商: FIN1108MTDX
Preliminary
www.fairchildsemi.com
4
F
Required Specifications:
1. When the true and complement LVDS outputs (having
a 100
connected between outputs) are connected to
3.75k
resistors and the common point of those
3.75k
resistors are connected to a voltage source
that sweeps from 0V to 2.4V, the DC V
OD
and
V
OD
are still maintained (see Figure 1).
2. When the true and complement LVDS inputs are con-
nected together to a voltage source that sweeps from
0V to 2.4V with respect to the common ground, then
the absolute value of the difference in input leakage
current is less than 6
μ
A (see Figure 2)
3. Pull-down resistor is required on the enable (EN) input.
4. Human Body Model ESD and Machine Model ESD
should be measured using MIL-STD-883C method
3015.7 standard.
5. Latch-up immunity should be tested to the EIA/JEDEC
standard number 78 (EIA/JESD78).
6. When the true and complement LVDS outputs are con-
nected with 49.9
resistors each to common point,
then the common point does not vary by more than
150mV under all process, temperature, and voltage
conditions when the outputs switch either from
LOW-to-HIGH or from HIGH-to-LOW (see Figure 3,
C
L
=
board
+
pin stray capacitance)
7. When the LVDS inputs are not driven either in High
Impedance, shorted together, or terminated with a
resistor, the outputs go the HIGH state (D
OUT
+
=
H,
D
OUT
=
L) and the LVDS inputs do not sink or source
more than 20
μ
A.
FIGURE 1. Common Mode Supply Test Circuit
FIGURE 2. Receiver Input Balance Measurements
FIGURE 3. Dynamic V
OS
Test Circuit and Waveforms
FIGURE 4. Differential Receiver Voltage Definitions and
Propagation I and Transition Time Test Circuit
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