參數(shù)資料
型號(hào): FIN1048MTC
英文描述: LINE RECEIVER|QUAD|DIFFERENTIAL|TSSOP|16PIN|PLASTIC
中文描述: 線路接收器|四|差|采用TSSOP | 16PIN |塑料
文件頁(yè)數(shù): 1/8頁(yè)
文件大小: 324K
代理商: FIN1048MTC
Preliminary
2001 Fairchild Semiconductor Corporation
DS500506
www.fairchildsemi.com
November 2000
Revised January 2001
F
FIN1019
3.3V LVDS High Speed Differential Driver/Receiver
(Preliminary)
General Description
This driver and receiver pair are designed for high speed
interconnects utilizing Low Voltage Differential Signaling
(LVDS) technology. The driver translates LVTTL signals to
LVDS levels with a typical differential output swing of
350mV and the receiver translates LVDS signals, with a
typical differential input threshold of 100mV, into LVTTL
levels. LVDS technology provides low EMI at ultra low
power dissipation even at high frequencies. This device is
ideal for high speed clock or data transfer.
Features
I
Greater than 400Mbs data rate
I
3.3V power supply operation
I
0.5ns maximum differential pulse skew
I
2.5ns maximum propagation delay
I
Low power dissipation
I
Power OFF protection
I
100mV receiver input sensitivity
I
Fail safe protection open-circuit, shorted and terminated
conditions
I
Meets or exceeds the TIA/EIA-644 LVDS standard
I
Flow-through pinout simplifies PCB layout
I
14-Lead SOIC and TSSOP packages save space
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Function Table
H
=
HIGH Logic Level
Z
=
High Impedance
L
=
LOW Logic Level
Fail Safe
=
Open, Shorted, Terminated
X
=
Don’t Care
Connection Diagram
Pin Descriptions
Order Number
FIN1019M
FIN1019MTC
Package Number
M14A
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Inputs
Outputs
RI
+
L
H
X
Fail Safe Condition
DI
L
H
X
Open
Circuit or Z
RI
H
L
X
RE
L
L
H
L
RO
L
H
Z
H
DE
H
H
L
H
DO
+
L
H
Z
L
DO
H
L
Z
H
Pin Name
DI
DO
+
DO
DE
RI
+
RI
RO
Description
LVTTL Data Input
Non-inverting LVDS Output
Inverting LVDS Output
Driver Enable (LVTTL, Active HIGH)
Non-Inverting LVDS Input
Inverting LVDS Input
LVTTL Receiver Output
RE
V
CC
GND
Receiver Enable (LVTTL, Active LOW)
Power Supply
Ground
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