參數(shù)資料
型號: FGE
文件頁數(shù): 1/4頁
文件大小: 65K
代理商: FGE
TL/U/10481
A
June 1989
ASIC
FGE Series ECL Gate Arrays
General Description
These advanced ECL gate arrays, ranging from 100 to 6300
equivalent gates, offer the system designer greater speed,
gate density, functional flexibility and temperature ranges
than standard F10K and F100K ECL families.
With system clock frequencies up to 600 MHz in some appli-
cations and a 225-ps typical macro propagation delay, the
FGE Series is especially well-suited for such high-perform-
ance applications as mainframe and supermini computers,
fiber-optic communications, as well as many military and
aerospace systems.
The FGE Series utilizes a cell-based, two-level series gate
(cascade) circuit structure which provides greater logic com-
plexity and reduces power levels compared to single-level
gating. An extensive macro library, common to all FGE ar-
rays, contains more than 80 SSI/MSI logic functions and
100 supporting I/O macros. Additionally, internal macros
may be grouped to form reusable ‘‘soft macros’’ with even
greater complexity functions.
All National ECL gate arrays feature CAD programmable
speed/power options that allow the designer to maximize
performance by individually assigning the switching speed
and output drive currents for each internal macro. The
speed/power feature provides maximum ECL speed where
needed yet allows overall chip power to remain at air-coola-
ble levels.
The FGE6300 utilizes slight process enhancements to
achieve a 30% power-per-gate reduction over other FGE
Series gate arrays. Thus, with 80% utilization of gates speci-
fied at high power, the FGE6300 dissipates about 13W.
Lower power settings and use of on-chip internal termina-
tion to
b
2V can reduce the total power dissipation to as
little as 5W. A proprietary multi-layer 301 pin with controlled-
impedance pin grid array package accommodates mounting
of decoupling capacitors on the package to reduce noise.
All FGE Series products interface with F100K or F10K ECL
SSI, MSI and LSI components and, in addition, the
FGE2500 is fuly FAST
TM
/TTL compatible. The FGE2500
TTL interface eliminates requirements for separate off-chip
signal converters in mixed logic level systems, thereby re-
sulting in reduced board space and cost, as well as avoiding
the performance and reliability penalties associated with off-
chip signal converters.
Features
Y
100, 680, 2500, 2840 and 6300 equivalent gates
Y
Proven 1.5 micron FAST-Z Fine-Line process
Y
System clock frequency up to 600 MHz
Y
Typical internal logic performance (2-input OR)
FGE6300
225 ps
@
5.2 mW
300 ps
@
2.7 mW
570 ps
@
1.3 mW
Other FGE Series Arrays
225 ps
@
9 mW
300 ps
@
4.8 mW
570 ps
@
2.5 mW
Y
CAD programmable speed/power options
Y
F100K or F10K ECL compatible I/Os
Y
Mixable TTL/ECL I/Os (FGE2500)
Y
Allows large number of unbalanced simultaneously
switching outputs
Specification Summary
Military Capability
Yes
Fabrication
Technology
ECL Fine Line
FAST-Z Gate Array
Gate Lengths &
Routing Layers
1.5
m
m, Three Layers
Gate Range
50–6,300
Typical Delay
225–570 ps
FAST
TM
is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
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