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參數(shù)資料
| 型號： | FC15A140CC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 382K |
| 代理商： | FC15A140CC |
FC15A140
5/16
FC15A140 BLOCK DIAGRAM
line select
PCLK
SHUTTER
RESET
AVIDEO
(1,1)
(30, 280)
sensor array
column
amplifier
& mux
column
select
SCLK
GAIN
OFFSET
LCLK
FCLK
FPL
PIN DESCRIPTION
Pin type
Pad
DIL
Name
Function
Ground
9
17
11
14
FPL
TEST
Front plane input. Must be grounded.
Test pin. Must be grounded.
Ground
14
16
GND_LOG
Digital ground
Ground
15
13
15
12
GND_ANA
G
Analog ground
Buffer ground
Ground
13
12
GND_BUF
Buffer ground
(note: all ground nodes connected via substrate)
Power
11
12
10
18
17
19
VDD_LOG
VDD_BUF
VDD_ANA
Digital power supply
Buffer power supply
Analog power supply
Analog input
7
10
OFFSET
Amplifier reference voltage. Must be externally
adjusted to 2.5v.
Digital input
4
16
6
5
13
4
9
PCLK
RESET
GAIN
SHUTTER
Pixel clock input
Shift register reset input. Active high.
Programable gain. Low: nominal, high: divided by 2.
Connected to VCC.
Digital output
1
3
2
7
6
8
SCLK
LCLK
FCLK
Sample clock output: data is ready on rising edge.
SCLK is PCLK delayed.
To be connected to the sample clock of ADC.
Line clock output. High at the beginning of a line.
Frame clock output. High during first line output.
Analog output
8
3
AVIDEO
Analog video output.
To be connected to the input of the ADC.
DIE MECHANICAL INFORMATION :
Mask set reference
VG20A
. . . . . . . . . . . . .
Die size
2.410 x 17.000 mm
. . . . . . . . . . . . . . . . . . . . . . .
Pad size
100 x 100
mm
. . . . . . . . . . . . . . . . . . . . . .
Die thickness
660
mm
. . . . . . . . . . . . . . . . . .
Metallization
Ti
(front side)
. . . . . . . . . . . . . . . . . . .
Poly (back side)
Passivation/coating
TBD
. . . . . . . . . . . . .
Revision
A
. . . . . . . . . . . . . . . . . . . . . .
Back side potential
GND
. . . . . . . . . . . . .
Transistor count
38860
. . . . . . . . . . . . . . .
Die attach
Epoxy
. . . . . . . . . . . . . . . . . . . . .
Bond wire
AlSi/Ti
. . . . . . . . . . . . . . . . . . . . .
VDD_ANA
VDD_LOG
VDD_BUF
GND_BUF
GND_LOG
GND_ANA
RESET
(17) TEST
SCLK (Pad 1)
FCLK
PCLK
LCLK
SHUTTER
GAIN
FPL AVIDEO
OFFSET
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