參數(shù)資料
型號(hào): FBL22033
廠商: NXP Semiconductors N.V.
英文描述: 3.3V BTL 8-bit latched/registered/pass-thru Futurebus universal interface transceiver
中文描述: 3.3橋接8位鎖存/注冊(cè)/直通Futurebus通用接口的收發(fā)器
文件頁數(shù): 9/14頁
文件大?。?/td> 147K
代理商: FBL22033
Philips Semiconductors
Product specification
FBL22033
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver with 30
termination
1999 Apr 15
9
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (B TO A)
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= +25
°
C, V
CC
= 3.3V
T
amb
= –40 to +85
°
C,
CC
= 3.3V
±
10%
MIN
UNIT
MIN
TYP
MAX
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PHZ
t
PZH
t
PHZ
Propagation delay,
Bn to An through mode
2.2
2.9
4.6
5.4
7.0
7.8
1.6
2.5
8.1
9.2
ns
Propagation delay,
Bn to An transparent latch
3.1
3.0
5.6
5.6
8.1
8.1
2.1
2.8
9.6
9.4
ns
Propagation delay,
LCAB to An latch
1.9
1.7
3.7
3.5
6.1
5.2
1.3
1.2
7.5
6.0
ns
Propagation delay,
LCAB to An register
1.7
2.3
3.9
4.3
6.0
6.2
1.1
1.9
7.1
7.0
ns
Propagation delay,
SABX to An inverting
2.1
2.6
4.5
4.9
6.8
7.1
1.6
2.1
8.2
7.7
ns
Propagation delay,
SABX to An non-inverting
1.2
1.9
4.1
4.3
9.2
6.6
1.0
1.6
9.9
7.5
ns
Propagation delay,
AIn to AOn loopback
2.2
2.2
4.5
4.5
6.7
6.7
1.5
1.6
7.9
7.8
ns
Propagation delay,
LPBK to An non-inverting or inverting
1.7
1.2
4.6
5.4
7.5
9.6
1.5
1.0
9.3
11.1
ns
Propagation delay,
OEA to An
2.1
2.3
4.6
5.2
6.8
8.1
1.8
2.0
7.7
9.2
ns
Propagation delay,
OEA to An
2.0
1.2
4.5
3.0
7.0
4.7
1.8
1.0
7.6
5.3
ns
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