參數(shù)資料
型號： FB2033
廠商： NXP Semiconductors N.V.
英文描述： 8-bit latched/registered/pass-thru Futurebus universal interface transceiver
中文描述： 8位鎖存/注冊/直通Futurebus通用接口的收發(fā)器
文件頁數(shù)： 7/10頁
文件大?。?/td> 173K
代理商： FB2033
Philips Semiconductors
Product specification
FB2033
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
1995 May 25
7
LIVE INSERTION SPECIFICATIONS
SYMBOL
PARAMETER
LIMITS
NOM
UNIT
MIN
MAX
V
BIASV
Bias pin voltage
V
CC
= 0 to 5.25V, Bn = 0 to 2.0V
V
= 0 to 4.75V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
4.5
5.5
V
I
BIASV
Bias pin DC current
1
mA
V
CC
= 4.5 to 5.5V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
10
μ
A
V
Bn
I
LM
I
HM
Bus voltage during pre-bias
B0 – B8 = 0V, Bias V = 5.0V
1.62
2.1
V
Fall current during pre-bias
B0 – B8 = 2V, Bias V = 4.5 to 5.5V
1
μ
A
μ
A
Rise current during pre-bias
B0 – B8 = 1V, Bias V = 4.5 to 5.5V
-1
I
Bn
Peak bus current during
insertion
V
CC
= 0 to 5.25V, B0 – B8 = 0 to 2.0V,
Bias V = 4.5 to 5.5V, OEB0 = 0.8V, t
r
= 2ns
V
CC
= 0 to 5.25V, OEB0 = 0.8V
V
CC
= 0 to 2.2V, OEB0 = 0 to 5V
V
CC
= 5.0V
10
mA
I
OL
Power up current
100
μ
A
100
t
GR
Input glitch rejection
1.0
1.35
ns
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
A PORT LIMITS
UNIT
T
amb
= +25
°
C, V
= 5V,
L
= 50pF, R
L
= 500
T
amb
= 0 to 70
°
C,
V
= 5V
±
10%,
C
L
= 50pF, R
L
= 500
MIN
TYP
MAX
MIN
MAX
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
TLH
t
THL
t
SK
(o)
Maximum clock frequency
Waveform 4
100
150
100
MHz
Propagation delay (thru mode)
Bn to AOn
Waveform 1, 2
2.2
2.0
4.3
4.1
6.0
6.0
2.0
1.8
7.0
7.0
ns
Propagation delay (transparent latch)
Bn to AOn
Waveform 1, 2
1.5
2.4
4.5
4.4
6.5
6.5
1.0
2.0
7.5
7.5
ns
Propagation delay
LCBA to AOn
Waveform 1, 2
2.0
2.2
3.8
4.3
5.5
6.0
1.8
1.7
6.0
6.5
ns
Propagation delay
SBAn to AOn
Waveform 1, 2
1.4
1.4
2.9
3.1
5.0
5.5
1.0
1.0
6.0
6.5
ns
Propagation delay (Loopback mode)
AIn to AOn
Waveform 1, 2
2.0
2.0
3.8
3.9
6.0
6.0
2.8
2.3
7.0
7.0
ns
Propagation delay (Loopback mode)
Loopback to AOn
Waveform 1, 2
1.2
1.2
3.4
3.2
5.0
5.5
1.0
1.0
6.0
6.5
ns
Output enable time from High or Low
OEA to AOn
Waveform 5, 6
1.0
2.6
3.1
4.0
5.1
5.5
1.0
2.4
5.5
5.8
ns
Output disable time to High or Low
OEA to AOn
Waveform 5, 6
1.0
1.0
3.5
3.3
5.0
4.6
1.7
1.7
5.6
5.2
ns
Output transition time, AOn Port
10% to 90%, 90% to 10%
Output to output skew, A port
1
Test Circuit and
Waveforms
2.0
2.0
5.0
5.0
ns
Waveform 3
0.5
1.0
1.5
ns
t
SK
(p)
Pulse skew 2
t
PHL
– t
PLH
MAX
Waveform 2
0.3
1.0
1.5
ns
NOTES:
1. Bn to AOn propagation delays are extended for 5 nanoseconds following B port excursions above 3.1 volts.
2.
t
PN
actual – t
PM
actual
for any data input to output path compared to any other data input to output path where N and M are either LH or HL.
Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.).
3. t
SK
(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
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FB2033K 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT TTL/BTL REGISTERED TRANSCEIVER
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