?2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7930C " Rev. 1.0.2
14
V OU   T
P  F  C
+
-
I N  V
1
C  O  M  P
3
C   l a  m   p  
C   i r c  u  i t
+
-
V
RE  F
S   t a  i r
S   t e  p
T  H   D   - O   p  t i m   i z  e  d  
S   a  w   t o  o  t h  
G   e  n  e  r a  t o  r
S  a w  t o o t h
M  O  S  F E  T O  f f
R  1
C  1
C  2
1V
6  . 2  V
Figure 32.    Control Circuit
Unlike a conventional voltage-mode PWM controller,
FAN7930C turns on the MOSFET at the falling edge of
ZCD signal. The ON instant is determined by the
external signal and the turn-on time lasts until the error
amplifier output (V
COMP
) and sawtooth waveform meet.
When load is heavy, output voltage decreases, scaled
output    decreases,    COMP    voltage    increases    to
compensate low output, turn-on time lengthens to give
more inductor turn-on time, and increased inductor
current raises the output voltage. This is how a PFC
negative feedback controller regulates output.
The maximum of V
COMP
is limited to 6.5 V, which
dictates the maximum turn-on time. Switching stops
when V
COMP
is lower than 1.0 V.
Z C  D     a  f t e  r C   O   M   P  A   R   A   T  O   R
V
CO   M   P
&   S  a  w  t o  o  t h
M  O  S  F  E  T   g  a  t e
s
/
V
1
5
5
.
Figure 33.    Turn-On Time Determination
The roles of PFC controller are regulating output voltage
and input current shaping to increase power factor. Duty
control based on the output voltage should be fast
enough to compensate output voltage dip or overshoot.
For the power factor, however, the control loop must not
react to the fluctuating AC input voltage. These two
requirements   conflict;   therefore,   when   designing   a
feedback loop, the feedback loop should be least ten
times   slower   than   AC   line   frequency.   That   slow
response is made by C1 at the compensator. R1 makes
gain boost around operation region and C2 attenuates
gain at higher frequency. Boost gain by R1 helps raise
the response time and improves phase margin.
Fr e q .
C
1
R
1
P r o p o r t i o n a l
g a i n
C   2
I n t e g r a t o r
H  i g h - F r e q u e n c y
Ni   F i l  r
G  a i n
Figure 34.    Compensators Gain Curve
For the transconductance error amplifier side, gain
changes based on differential input. When the error is
large, gain is large to suppress the output dip or peak
quickly. When the error is small, low gain is used to
improve power factor performance.
I
CO M P
Po w e rin g
B ra k in g
m
h
o
5
0
m
h
o
1
5
Figure 35.    Gain Characteristic
7. Soft-Start: When V
CC
reaches V
START
, the internal
reference voltage is increased like a stair step for 5 ms.
As a result, V
COMP
is also raised gradually and MOSFET
turn-on time increases smoothly. This reduces voltage
and current stress on the power switch during startup.
V
R    E   F
S   S
g
M
V
I N    V
=  0  . 4  V
I  S   O    U    R    C    E
C    O    M    P
V
C    O    M    P
I
S   O    U    R    C    E
C    O    M    P   
R
C    O    M    P
=  V
C    O    M    P
( V
R    E   F
S   S
- V
I N    V
)
g
M
=  I
S   O    U    R    C    E
C    O    M    P
V
R    E   F
E   N    D
=  2  . 5  V
5  m   s
V
C    C
V
S   T   A   R    T
=  1  2  V
Figure 36.    Soft-Start Sequence
8. Startup without Overshoot: Feedback control speed
of PFC is quite slow. Due to the slow response, there is
a gap between output voltage and feedback control.
That is why over-voltage protection (OVP) is critical at
the PFC controller and voltage dip caused by fast load
changes from light to heavy is diminished by a bulk
capacitor.   OVP   is   triggered   during   startup   phase.
Operation on and off by OVP at startup may cause
audible noise and can increase voltage stress at startup,